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Low-power design and power-aware ver...

Khondkar, Progyna.

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Low-power design and power-aware verification

Record Type:	Electronic resources : Monograph/item
Title/Author:	Low-power design and power-aware verification/ by Progyna Khondkar.
Author:	Khondkar, Progyna.
Published:	Cham :Springer International Publishing : : 2018.,
Description:	xv, 155 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References.
Contained By:	Springer eBooks
Subject:	Low voltage integrated circuits - Design and construction. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-66619-8
ISBN:	9783319666198

Low-power design and power-aware verification
Khondkar, Progyna.

Low-power design and power-aware verification[electronic resource] /by Progyna Khondkar. - Cham :Springer International Publishing :2018. - xv, 155 p. :ill. (some col.), digital ;24 cm.

1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References.

Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF) Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.

ISBN: 9783319666198

Standard No.: 10.1007/978-3-319-66619-8doiSubjects--Topical Terms:

699876
Low voltage integrated circuits
--Design and construction.

LC Class. No.: TK7874.66 / .K46 2018

Dewey Class. No.: 621.3815

Low-power design and power-aware verification
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505 0 $a 1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References.
520 $a Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF) Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.
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