東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

High-level estimation and exploratio...

Wang, Zheng.

Linked to FindBook

Google Book

Amazon

博客來

High-level estimation and exploration of reliability for multi-processor system-on-chip

Record Type:	Electronic resources : Monograph/item
Title/Author:	High-level estimation and exploration of reliability for multi-processor system-on-chip/ by Zheng Wang, Anupam Chattopadhyay.
Author:	Wang, Zheng.
other author:	Chattopadhyay, Anupam.
Published:	Singapore :Springer Singapore : : 2018.,
Description:	xx, 197 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:	Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.
Contained By:	Springer eBooks
Subject:	Systems on a chip. -
Online resource:	http://dx.doi.org/10.1007/978-981-10-1073-6
ISBN:	9789811010736

High-level estimation and exploration of reliability for multi-processor system-on-chip
Wang, Zheng.

High-level estimation and exploration of reliability for multi-processor system-on-chip[electronic resource] /by Zheng Wang, Anupam Chattopadhyay. - Singapore :Springer Singapore :2018. - xx, 197 p. :ill. (some col.), digital ;24 cm. - Computer architecture and design methodologies,2367-3478. - Computer architecture and design methodologies..

Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

ISBN: 9789811010736

Standard No.: 10.1007/978-981-10-1073-6doiSubjects--Topical Terms:

729732
Systems on a chip.

LC Class. No.: TK7895.E42

Dewey Class. No.: 006.22

High-level estimation and exploration of reliability for multi-processor system-on-chip
LDR:01855nmm a2200325 a 4500 001 2130562
003 DE-He213
005 20170623164403.0
006 m d
007 cr nn 008maaau
008 181005s2018 si s 0 eng d
020 $a 9789811010736 $q (electronic bk.)
020 $a 9789811010729 $q (paper)
024 7 $a 10.1007/978-981-10-1073-6 $2 doi
035 $a 978-981-10-1073-6
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.E42
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 006.22 $2 23
090 $a TK7895.E42 $b W246 2018
100 1 $a Wang, Zheng. $3 660235
245 1 0 $a High-level estimation and exploration of reliability for multi-processor system-on-chip $h [electronic resource] / $c by Zheng Wang, Anupam Chattopadhyay.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2018.
300 $a xx, 197 p. : $b ill. (some col.), digital ; $c 24 cm.
490 1 $a Computer architecture and design methodologies, $x 2367-3478
505 0 $a Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.
520 $a This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
650 0 $a Systems on a chip. $3 729732
650 0 $a Fault-tolerant computing. $3 649213
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Performance and Reliability. $3 893430
650 2 4 $a Electronic Circuits and Devices. $3 1245773
700 1 $a Chattopadhyay, Anupam. $3 1001810
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
830 0 $a Computer architecture and design methodologies. $3 2203505
856 4 0 $u http://dx.doi.org/10.1007/978-981-10-1073-6
950 $a Engineering (Springer-11647)