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ASIC/SoC functional design verificat...

Mehta, Ashok B.

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ASIC/SoC functional design verification = a comprehensive guide to technologies and methodologies /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	ASIC/SoC functional design verification/ by Ashok B. Mehta.
其他題名:	a comprehensive guide to technologies and methodologies /
作者:	Mehta, Ashok B.
出版者:	Cham :Springer International Publishing : : 2018.,
面頁冊數:	xxxi, 328 p. :ill., digital ;24 cm.
內容註:	Chapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based.
Contained By:	Springer eBooks
標題:	Application-specific integrated circuits - Design. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-59418-7
ISBN:	9783319594187

ASIC/SoC functional design verification = a comprehensive guide to technologies and methodologies /
Mehta, Ashok B.

ASIC/SoC functional design verificationa comprehensive guide to technologies and methodologies /[electronic resource] :by Ashok B. Mehta. - Cham :Springer International Publishing :2018. - xxxi, 328 p. :ill., digital ;24 cm.

Chapter 1.Introduction -- Chapter 2.Functional Verification- Challeenges and Solution -- Chapter 3.SystemVerilog Paradigm -- Chapter 4. UVM -- Chapter 5.CRV -- Chapter 6.SVA -- Chapter 7.SFC -- Chapter 8.CDC -- Chapter 9.Low Power Verification -- Chapter 10. Static Verification -- Chapter 11.ESL -- Chapter 12. Hardware/Software Co-verification -- Chapter 13 -- Analog Mixed Signals Verification -- Chapter 14 -- SOC Interconnect Verification -- Chapter 15. The Complete Product Design Lifecycle -- Chapter 16. Voice Over IP -- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based -- Chapter 18. Cache Memory Subsystem Verification: ISS Based.

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.

ISBN: 9783319594187

Standard No.: 10.1007/978-3-319-59418-7doiSubjects--Topical Terms:

3220634
Application-specific integrated circuits
--Design.

LC Class. No.: TK7874.6

Dewey Class. No.: 621.3815

ASIC/SoC functional design verification = a comprehensive guide to technologies and methodologies /
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