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Quantum transport and dielectric res...

Fang, Jingtian.

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Quantum transport and dielectric response of nanometer scale transistors using empirical pseudopotentials.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Quantum transport and dielectric response of nanometer scale transistors using empirical pseudopotentials./
作者:	Fang, Jingtian.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2016,
面頁冊數:	144 p.
附註:	Source: Dissertation Abstracts International, Volume: 77-11(E), Section: B.
Contained By:	Dissertation Abstracts International77-11B(E).
標題:	Materials science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10113810
ISBN:	9781339768670

Quantum transport and dielectric response of nanometer scale transistors using empirical pseudopotentials.
Fang, Jingtian.

Quantum transport and dielectric response of nanometer scale transistors using empirical pseudopotentials. - Ann Arbor : ProQuest Dissertations & Theses, 2016 - 144 p.

Source: Dissertation Abstracts International, Volume: 77-11(E), Section: B.

Thesis (Ph.D.)--The University of Texas at Dallas, 2016.

As transistors, the most basic component of central processing units (CPU) in all electronic products, are scaling down to the nanometer scale, quantum mechanical effects must be studied to investigate their performance. A formalism to treat quantum electronic transport at the nanometer scale based on empirical pseudopotentials is presented in this dissertation. We develop the transport equations and show the expressions to calculate the device characteristics, such as device current and charge density. We apply this formalism to study ballistic transport in a gate-all-around (GAA) silicon nanowire field-effect transistor (FET) with a body-size of 0.39 nm, a gate length of 6.52 nm, and an effective oxide thickness of 0.43 nm. Simulation results show that this device exhibits a subthreshold slope (SS) of &sim;66 mV/decade and a drain-induced barrier-lowering of ~2.5 mV/V. This formalism is also applied to assess the ballistic performance of FETs with armchair-edge graphene nanoribbon (aGNRs) and silicon nanowire (SiNWs) channels and with gate lengths ranging from 5 nm to 15 nm. The device characteristics of the transistors with a 5 nm gate length are compared. Source-to-drain tunneling effects are investigated for SiNWFETs and GNRFETs by comparing the I-V characteristics of each respective transistor with different channel lengths.

ISBN: 9781339768670Subjects--Topical Terms:

543314
Materials science.

Quantum transport and dielectric response of nanometer scale transistors using empirical pseudopotentials.
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245 1 0 $a Quantum transport and dielectric response of nanometer scale transistors using empirical pseudopotentials.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2016
300 $a 144 p.
500 $a Source: Dissertation Abstracts International, Volume: 77-11(E), Section: B.
500 $a Adviser: Massimo V. Fischetti.
502 $a Thesis (Ph.D.)--The University of Texas at Dallas, 2016.
520 $a As transistors, the most basic component of central processing units (CPU) in all electronic products, are scaling down to the nanometer scale, quantum mechanical effects must be studied to investigate their performance. A formalism to treat quantum electronic transport at the nanometer scale based on empirical pseudopotentials is presented in this dissertation. We develop the transport equations and show the expressions to calculate the device characteristics, such as device current and charge density. We apply this formalism to study ballistic transport in a gate-all-around (GAA) silicon nanowire field-effect transistor (FET) with a body-size of 0.39 nm, a gate length of 6.52 nm, and an effective oxide thickness of 0.43 nm. Simulation results show that this device exhibits a subthreshold slope (SS) of &sim;66 mV/decade and a drain-induced barrier-lowering of ~2.5 mV/V. This formalism is also applied to assess the ballistic performance of FETs with armchair-edge graphene nanoribbon (aGNRs) and silicon nanowire (SiNWs) channels and with gate lengths ranging from 5 nm to 15 nm. The device characteristics of the transistors with a 5 nm gate length are compared. Source-to-drain tunneling effects are investigated for SiNWFETs and GNRFETs by comparing the I-V characteristics of each respective transistor with different channel lengths.
520 $a While a uniform dielectric constant is assumed in solving Poisson equation for the devices simulated above, the knowledge of the atomistic (i.e., local) dielectric permittivity that considers the atomistic electron distribution and quantum-confinement effect is necessary to treat the electrostatic properties accurately. The local permittivity can also provide information about the dielectric property at the interfaces. We use the random-phase approximation, first-order perturbation theory, and empirical pseudopotentials to calculate the static polarizability, susceptibility, and dielectric response function in graphene and GNRs. While the artifacts of the supercell method prevent us from calculating the longitudinal atomistic dielectric permittivity directly through the dielectric response function, we propose a microscopic Poisson equation which relates the external charge density to the total potential through the polarizability (also called density-density response function). Solving this equation permits the calculation of an atomistic dielectric tensor for anisotropic crystals. We show the atomistic distribution of the local dielectric tensor for an anisotropic GNR. This quantity can be used to solve Poisson equation properly for a self-consistent atomistic device simulation accounting for quantum effects on the nanodielectric.
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650 4 $a Electrical engineering. $3 649834
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710 2 $a The University of Texas at Dallas. $b Materials Science and Engineering. $3 3168649
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