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Low-power CMOS digital pixel imagers...

Margarit, Josep Maria.

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Low-power CMOS digital pixel imagers for high-speed uncooled PbSe IR applications

Record Type:	Electronic resources : Monograph/item
Title/Author:	Low-power CMOS digital pixel imagers for high-speed uncooled PbSe IR applications/ by Josep Maria Margarit.
Author:	Margarit, Josep Maria.
Published:	Cham :Springer International Publishing : : 2017.,
Description:	xxi, 173 p. :ill., digital ;24 cm.
[NT 15003449]:	Introduction -- Frame-Based Smart IR Imagers -- Frame-Free Compact-Pitch IR Imagers -- Pixel Test Chips in 0.35mm and 0.15mm CMOS Technologies -- Imager Test Chips in 2.5mm, 0.35mm and 0.15mm CMOS Technologies -- Conclusions.
Contained By:	Springer eBooks
Subject:	Infrared imaging. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-49962-8
ISBN:	9783319499628

Low-power CMOS digital pixel imagers for high-speed uncooled PbSe IR applications
Margarit, Josep Maria.

Low-power CMOS digital pixel imagers for high-speed uncooled PbSe IR applications[electronic resource] /by Josep Maria Margarit. - Cham :Springer International Publishing :2017. - xxi, 173 p. :ill., digital ;24 cm. - Springer theses,2190-5053. - Springer theses..

Introduction -- Frame-Based Smart IR Imagers -- Frame-Free Compact-Pitch IR Imagers -- Pixel Test Chips in 0.35mm and 0.15mm CMOS Technologies -- Imager Test Chips in 2.5mm, 0.35mm and 0.15mm CMOS Technologies -- Conclusions.

This book describes the development of a new low-cost medium wavelength IR (MWIR) monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapor phase deposition (VPD) PbSe-based MWIR detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. In order to fulfill the operational requirements of VPD PbSe, this work proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.

ISBN: 9783319499628

Standard No.: 10.1007/978-3-319-49962-8doiSubjects--Topical Terms:

710743
Infrared imaging.

LC Class. No.: TA1570

Dewey Class. No.: 621.3672

Low-power CMOS digital pixel imagers for high-speed uncooled PbSe IR applications
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100 1 $a Margarit, Josep Maria. $3 3219576
245 1 0 $a Low-power CMOS digital pixel imagers for high-speed uncooled PbSe IR applications $h [electronic resource] / $c by Josep Maria Margarit.
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505 0 $a Introduction -- Frame-Based Smart IR Imagers -- Frame-Free Compact-Pitch IR Imagers -- Pixel Test Chips in 0.35mm and 0.15mm CMOS Technologies -- Imager Test Chips in 2.5mm, 0.35mm and 0.15mm CMOS Technologies -- Conclusions.
520 $a This book describes the development of a new low-cost medium wavelength IR (MWIR) monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapor phase deposition (VPD) PbSe-based MWIR detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. In order to fulfill the operational requirements of VPD PbSe, this work proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.
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