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Electromigration inside logic cells ...

Posser, Gracieli.

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Electromigration inside logic cells = modeling, analyzing and mitigating signal electromigration in NanoCMOS /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Electromigration inside logic cells/ by Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis.
其他題名:	modeling, analyzing and mitigating signal electromigration in NanoCMOS /
作者:	Posser, Gracieli.
其他作者:	Sapatnekar, Sachin S.
出版者:	Cham :Springer International Publishing : : 2017.,
面頁冊數:	xx, 118 p. :ill., digital ;24 cm.
內容註:	Chapter 1. Introduction -- Chapter 2. State of the Art -- Chapter 3. Modeling Cell-internal EM -- Chapter 4. Current Calculation -- Chapter 5. Experimental Setup -- Chapter 6.Results -- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers -- Chapter 8. Conclusions.
Contained By:	Springer eBooks
標題:	Logic circuits. -
電子資源:	http://dx.doi.org/10.1007/978-3-319-48899-8
ISBN:	9783319488998

Electromigration inside logic cells = modeling, analyzing and mitigating signal electromigration in NanoCMOS /
Posser, Gracieli.

Electromigration inside logic cellsmodeling, analyzing and mitigating signal electromigration in NanoCMOS /[electronic resource] :by Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis. - Cham :Springer International Publishing :2017. - xx, 118 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. State of the Art -- Chapter 3. Modeling Cell-internal EM -- Chapter 4. Current Calculation -- Chapter 5. Experimental Setup -- Chapter 6.Results -- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers -- Chapter 8. Conclusions.

This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics.

ISBN: 9783319488998

Standard No.: 10.1007/978-3-319-48899-8doiSubjects--Topical Terms:

527270
Logic circuits.

LC Class. No.: TK7868.L6

Dewey Class. No.: 621.395

Electromigration inside logic cells = modeling, analyzing and mitigating signal electromigration in NanoCMOS /
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