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Designing with Xilinx FPGAs = using ...

Churiwala, Sanjay.

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Designing with Xilinx FPGAs = using Vivado /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Designing with Xilinx FPGAs/ edited by Sanjay Churiwala.
Reminder of title:	using Vivado /
other author:	Churiwala, Sanjay.
Published:	Cham :Springer International Publishing : : 2017.,
Description:	x, 260 p. :ill., digital ;24 cm.
[NT 15003449]:	State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.
Contained By:	Springer eBooks
Subject:	Field programmable gate arrays. -
Online resource:	http://dx.doi.org/10.1007/978-3-319-42438-5
ISBN:	9783319424385

Designing with Xilinx FPGAs = using Vivado /
Designing with Xilinx FPGAsusing Vivado /[electronic resource] :edited by Sanjay Churiwala. - Cham :Springer International Publishing :2017. - x, 260 p. :ill., digital ;24 cm.

State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.

ISBN: 9783319424385

Standard No.: 10.1007/978-3-319-42438-5doiSubjects--Uniform Titles:

Vivado Design Suite.
Subjects--Topical Terms:

666370
Field programmable gate arrays.

LC Class. No.: TK7895.G36 / D47 2017

Dewey Class. No.: 621.395

Designing with Xilinx FPGAs = using Vivado /
LDR:01348nmm a2200301 a 4500 001 2088107
003 DE-He213
005 20161020123703.0
006 m d
007 cr nn 008maaau
008 171013s2017 gw s 0 eng d
020 $a 9783319424385 $q (electronic bk.)
020 $a 9783319424378 $q (paper)
024 7 $a 10.1007/978-3-319-42438-5 $2 doi
035 $a 978-3-319-42438-5
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.G36 $b D47 2017
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.395 $2 23
090 $a TK7895.G36 $b D457 2017
245 0 0 $a Designing with Xilinx FPGAs $h [electronic resource] : $b using Vivado / $c edited by Sanjay Churiwala.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a x, 260 p. : $b ill., digital ; $c 24 cm.
505 0 $a State of the Art Programmable Logic -- Vivado Design Tools -- IP Flows -- Gigabit Transceivers -- Memory Controllers -- Processor Options -- Vivado IP Integrator -- SysGen for DSP -- Synthesis -- C Based Design -- Simulation -- Clocking -- Stacked Silicon Interconnect -- Timing Closure -- Power Analysis and Optimization -- System Monitor -- Hardware Debug -- Emulation Using FPGAs -- Partial Reconfiguration & Hierarchical Design.
630 0 0 $a Vivado Design Suite. $3 3217568
650 0 $a Field programmable gate arrays. $3 666370
650 0 $a Computer-aided design. $3 531217
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 893838
700 1 $a Churiwala, Sanjay. $3 3217567
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-42438-5
950 $a Engineering (Springer-11647)