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Design, Model and Analysis of TSV-ba...

Charles, Gary.

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Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits./
Author:	Charles, Gary.
Description:	125 p.
Notes:	Source: Dissertation Abstracts International, Volume: 76-11(E), Section: B.
Contained By:	Dissertation Abstracts International76-11B(E).
Subject:	Electrical engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3710588
ISBN:	9781321865707

Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits.
Charles, Gary.

Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits. - 125 p.

Source: Dissertation Abstracts International, Volume: 76-11(E), Section: B.

Thesis (Ph.D.)--North Carolina State University, 2015.

In traditional design of power delivery networks (PDNs), the impedance property of the network is required to be less than the target impedance across a broad range of frequencies to ensure IR-drop is minimized and simultaneous switching noise (SSN) is suppressed. It is becoming increasingly more challenging to meet the electrical constraints and performance of modern integrated circuit (IC) design using conventional interconnect technology. However, three-dimensional (3-D) stacking using through-silicon via (TSV) technology has emerged as a viable solution to reduce interconnect delay, power supply noise and achieve heterogeneous IC module integration. A major advantage to using TSVs is the shortened interconnect path to pass data signals and deliver clean power at a fast rate between chips. A low impedance return path in the PDN guarantees negligible interference or noise into other sensitive timing and signaling circuits (e.g. signal generation circuits and PLLs). In an effort to keep up with scaling technology and robust PDN designs, TSV technology is a promising option relative to the other interconnect options available today.

ISBN: 9781321865707Subjects--Topical Terms:

649834
Electrical engineering.

Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits.
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100 1 $a Charles, Gary. $3 3182251
245 1 0 $a Design, Model and Analysis of TSV-based On-Chip PDN Interconnects for 3-D Integrated Circuits.
300 $a 125 p.
500 $a Source: Dissertation Abstracts International, Volume: 76-11(E), Section: B.
500 $a Adviser: Paul D. Franzon.
502 $a Thesis (Ph.D.)--North Carolina State University, 2015.
520 $a In traditional design of power delivery networks (PDNs), the impedance property of the network is required to be less than the target impedance across a broad range of frequencies to ensure IR-drop is minimized and simultaneous switching noise (SSN) is suppressed. It is becoming increasingly more challenging to meet the electrical constraints and performance of modern integrated circuit (IC) design using conventional interconnect technology. However, three-dimensional (3-D) stacking using through-silicon via (TSV) technology has emerged as a viable solution to reduce interconnect delay, power supply noise and achieve heterogeneous IC module integration. A major advantage to using TSVs is the shortened interconnect path to pass data signals and deliver clean power at a fast rate between chips. A low impedance return path in the PDN guarantees negligible interference or noise into other sensitive timing and signaling circuits (e.g. signal generation circuits and PLLs). In an effort to keep up with scaling technology and robust PDN designs, TSV technology is a promising option relative to the other interconnect options available today.
520 $a The research outlined in this dissertation focuses on the development, modeling and analysis of TSV-based PDN using on-chip decoupling capacitors. A combination of CAD simulation tools and analytical formulas was used to create the TSV-based PDN models and estimate its impedance property. The work outlined here focuses on a multi-tier chipstacking case-study. The case study is formulated around the effect different chip stacking topology has on the impedance property of TSV-based PDNs. The 3 distinct chip stacking topologies are listed as follows: (1) face-to-face (F2F); (2) face-to-back (F2B) and (3) back-to-back (B2B) chip stacking topologies. Quantitatively speaking, the study compared the impedance noise level between three stacking topologies and found the impedance noise of F2F chip stacking to be relatively lower than F2B and B2B. Among the power grid structure and power/ground TSV pair models presented in this research work, we also present and implement a metal-insulator-metal (MIM) capacitor model written as a complex impedance equation. Based on the physical dimensions of the MIM capacitor, we estimated the capacitance density (per unit area) range from 0.062 &fnof;F/mum 2 to 5.325 &fnof;F/mum2. We also modeled metal-oxide semiconductor (MOS) capacitors in this work. Conclusively, the research provides a modeling framework to design TSV-based PDNs with the intent of minimizing on-chip inductance. Overall, the goal is to advance the state-of-the-art in 3-D IC TSV-based PDN design.
590 $a School code: 0155.
650 4 $a Electrical engineering. $3 649834
650 4 $a Packaging. $3 585030
650 4 $a Electromagnetics. $3 3173223
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710 2 $a North Carolina State University. $3 1018772
773 0 $t Dissertation Abstracts International $g 76-11B(E).
790 $a 0155
791 $a Ph.D.
792 $a 2015
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3710588