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Characterization and Modeling of Non...

Barthol, Christopher John.

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Characterization and Modeling of Non-Volatile SONOS Semiconductor Memories with Gridded Capacitors.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Characterization and Modeling of Non-Volatile SONOS Semiconductor Memories with Gridded Capacitors./
作者:	Barthol, Christopher John.
面頁冊數:	292 p.
附註:	Source: Dissertation Abstracts International, Volume: 76-11(E), Section: B.
Contained By:	Dissertation Abstracts International76-11B(E).
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3710074
ISBN:	9781321859164

Characterization and Modeling of Non-Volatile SONOS Semiconductor Memories with Gridded Capacitors.
Barthol, Christopher John.

Characterization and Modeling of Non-Volatile SONOS Semiconductor Memories with Gridded Capacitors. - 292 p.

Source: Dissertation Abstracts International, Volume: 76-11(E), Section: B.

Thesis (Ph.D.)--The Ohio State University, 2015.

This item must not be sold to any third party vendors.

The demand for high-capacity, low-power memory is increasing rapidly as modern portable electronic devices boost performance while decreasing in size. Due to its many advantages over traditional floating gate memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type semiconductor memories and their various derivatives are the next step in the evolution of Non-Volatile Semiconductor Memory (NVSM) technology. As the SONOS cell size is decreased the gate stack has reached its limitations with silicon oxide used as the defacto oxide for both the blocking and tunneling layers. High K materials, which improve the electrical characteristics while maintaining a thick blocking or cap layer, have started to replace silicon dioxide. The change from a silicon dioxide that has seen over 60 years of development to new materials requires a rapid turnaround in the fabrication of devices as well as quick characterization of the gate stack.

ISBN: 9781321859164Subjects--Topical Terms:

649834
Electrical engineering.

Characterization and Modeling of Non-Volatile SONOS Semiconductor Memories with Gridded Capacitors.
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100 1 $a Barthol, Christopher John. $3 3176892
245 1 0 $a Characterization and Modeling of Non-Volatile SONOS Semiconductor Memories with Gridded Capacitors.
300 $a 292 p.
500 $a Source: Dissertation Abstracts International, Volume: 76-11(E), Section: B.
500 $a Adviser: Marvin White.
502 $a Thesis (Ph.D.)--The Ohio State University, 2015.
506 $a This item must not be sold to any third party vendors.
520 $a The demand for high-capacity, low-power memory is increasing rapidly as modern portable electronic devices boost performance while decreasing in size. Due to its many advantages over traditional floating gate memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type semiconductor memories and their various derivatives are the next step in the evolution of Non-Volatile Semiconductor Memory (NVSM) technology. As the SONOS cell size is decreased the gate stack has reached its limitations with silicon oxide used as the defacto oxide for both the blocking and tunneling layers. High K materials, which improve the electrical characteristics while maintaining a thick blocking or cap layer, have started to replace silicon dioxide. The change from a silicon dioxide that has seen over 60 years of development to new materials requires a rapid turnaround in the fabrication of devices as well as quick characterization of the gate stack.
520 $a We have fabricated gridded Metal-Aluminum Oxide-Nitride-Silicon Oxide-Silicon (MANOS) capacitors. The gridded capacitor structure allow carrier types other than what is originally present in the substrate. This structure is easier to fabricate while still allowing all characterization tests, such as speed write/erase and endurance tests, to be performed. This technique does not require ohmic contacts to the grid lines reducing the fabrication process. Two wafer sets have been created. One has an aluminum oxide block layer while the other has a hafnium/aluminum oxide blend.The capacitors have been fabricated on p-type silicon wafers with a resistivity of 20 &ohm; - cm. A grid structure with line widths of 5mum and line spacing ranging form 30mum to 300mum is defined and doped with phosphorous. The gate stacks consist of a high quality 2.4nm SiO2 tunnel oxide layer thermally grown in a triple-wall oxidation furnace, a 7.7nm silicon-rich nitride deposited by LPCVD, and the two sets of clocking oxides deposited by atomic layer deposition (ALD).
520 $a Various fundamental and dynamic electric characterization techniques such as Capacitance-Voltage, Linear Voltage Ramp, Speed Write/Erase, and Retention measurements have been completed on the gridded capacitor structure. The nuances of each test is described in detail. A flatband voltage tracking system has been created to aid in these measurements. We also discuss a set of simulation programs for charge trap non-volatile memories. The programs show excellent agreement with both full transistors and the gridded capacitor structure.
520 $a We also present a method to extract carrier mobility with the two terminal gridded capacitor structure where the silicon substrate is implanted with a grid structure of the opposite carrier type. We can extract the carrier mobility as a function of vertical electric field with a combination of Capacitance-Voltage(C-V) and Conductance-Voltage(G-V) measurements. In addition, the structure eliminates the need for source/drain contacts, which lends itself well to material systems where low resistance, source/drain contacts are difficult to implement and reduce device performance.
590 $a School code: 0168.
650 4 $a Electrical engineering. $3 649834
650 4 $a Condensed matter physics. $3 3173567
690 $a 0544
690 $a 0611
710 2 $a The Ohio State University. $b Electrical and Computer Engineering. $3 1672495
773 0 $t Dissertation Abstracts International $g 76-11B(E).
790 $a 0168
791 $a Ph.D.
792 $a 2015
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3710074