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Advanced MOSFET Designs and Implicat...

Shin, Changhwan.

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Advanced MOSFET Designs and Implications for SRAM Scaling.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Advanced MOSFET Designs and Implications for SRAM Scaling./
Author:	Shin, Changhwan.
Description:	108 p.
Notes:	Source: Dissertation Abstracts International, Volume: 74-01(E), Section: B.
Contained By:	Dissertation Abstracts International74-01B(E).
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3527065
ISBN:	9781267611840

Advanced MOSFET Designs and Implications for SRAM Scaling.
Shin, Changhwan.

Advanced MOSFET Designs and Implications for SRAM Scaling. - 108 p.

Source: Dissertation Abstracts International, Volume: 74-01(E), Section: B.

Thesis (Ph.D.)--University of California, Berkeley, 2011.

This item is not available from ProQuest Dissertations & Theses.

Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three-dimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.

ISBN: 9781267611840Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Advanced MOSFET Designs and Implications for SRAM Scaling.
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020 $a 9781267611840
035 $a (MiAaPQ)AAI3527065
035 $a AAI3527065
040 $a MiAaPQ $c MiAaPQ
100 1 $a Shin, Changhwan. $3 2200420
245 1 0 $a Advanced MOSFET Designs and Implications for SRAM Scaling.
300 $a 108 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-01(E), Section: B.
500 $a Adviser: Tsu-Jae King Liu.
502 $a Thesis (Ph.D.)--University of California, Berkeley, 2011.
506 $a This item is not available from ProQuest Dissertations & Theses.
506 $a This item must not be sold to any third party vendors.
506 $a This item must not be added to any third party search indexes.
520 $a Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three-dimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.
590 $a School code: 0028.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a University of California, Berkeley. $b Electrical Engineering & Computer Sciences. $3 1671057
773 0 $t Dissertation Abstracts International $g 74-01B(E).
790 $a 0028
791 $a Ph.D.
792 $a 2011
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3527065