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Advanced MOSFET Designs and Implicat...
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Shin, Changhwan.
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Advanced MOSFET Designs and Implications for SRAM Scaling.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Advanced MOSFET Designs and Implications for SRAM Scaling./
作者:
Shin, Changhwan.
面頁冊數:
108 p.
附註:
Source: Dissertation Abstracts International, Volume: 74-01(E), Section: B.
Contained By:
Dissertation Abstracts International74-01B(E).
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3527065
ISBN:
9781267611840
Advanced MOSFET Designs and Implications for SRAM Scaling.
Shin, Changhwan.
Advanced MOSFET Designs and Implications for SRAM Scaling.
- 108 p.
Source: Dissertation Abstracts International, Volume: 74-01(E), Section: B.
Thesis (Ph.D.)--University of California, Berkeley, 2011.
This item is not available from ProQuest Dissertations & Theses.
Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three-dimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.
ISBN: 9781267611840Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
Advanced MOSFET Designs and Implications for SRAM Scaling.
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Continued planar bulk MOSFET scaling is becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length, and thereby scaling of SRAM using minimum-size transistors is further challenging. This dissertation will discuss various advanced MOSFET designs and their benefits for extending density and voltage scaling of static memory (SRAM) arrays. Using three-dimensional (3-D) process and design simulations, transistor designs are optimized. Then, using an analytical compact model calibrated to the simulated transistor current-vs.-voltage characteristics, the performance and yield of six-transistor (6-T) SRAM cells are estimated. For a given cell area, fully depleted silicon-on-insulator (FD-SOI) MOSFET technology is projected to provide for significantly improved yield across a wide range of operating voltages, as compared with conventional planar bulk CMOS technology. Quasi-Planar (QP) bulk silicon MOSFETs are a lower-cost alternative and also can provide for improved SRAM yield. A more printable "notchless" QP bulk SRAM cell layout is proposed to reduce lithographic variations, and is projected to achieve six-sigma yield (required for terabit-scale SRAM arrays) with a minimum operating voltage below 1 Volt.
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