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Energy efficient computing through c...

Govindaraju, Venkatraman.

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Energy efficient computing through compiler assisted dynamic specialization.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Energy efficient computing through compiler assisted dynamic specialization./
作者:	Govindaraju, Venkatraman.
面頁冊數:	155 p.
附註:	Source: Dissertation Abstracts International, Volume: 76-01(E), Section: B.
Contained By:	Dissertation Abstracts International76-01B(E).
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3635253
ISBN:	9781321162332

Energy efficient computing through compiler assisted dynamic specialization.
Govindaraju, Venkatraman.

Energy efficient computing through compiler assisted dynamic specialization. - 155 p.

Source: Dissertation Abstracts International, Volume: 76-01(E), Section: B.

Thesis (Ph.D.)--The University of Wisconsin - Madison, 2014.

This item must not be sold to any third party vendors.

Due to the failure of threshold voltage scaling, per-transistor switching power is not scaling down at the pace of Moore's Law, causing the power density to rise for each successive generation. Consequently, computer architects need to improve the energy efficiency of microarchitecture designs to sustain the traditional performance growth. Hardware specialization or using accelerators is a promising direction to improve the energy efficiency without sacrificing performance. However, it requires disruptive changes in hardware and software including the programming model, applications, and operating systems. Moreover, specialized accelerators cannot help with the general purpose computing. Going forward, we need a solution that avoids such disruptive changes and can accelerate or specialize even general purpose workloads.

ISBN: 9781321162332Subjects--Topical Terms:

626642
Computer Science.

Energy efficient computing through compiler assisted dynamic specialization.
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500 $a Source: Dissertation Abstracts International, Volume: 76-01(E), Section: B.
500 $a Adviser: Karthikeyan Sankaralingam.
502 $a Thesis (Ph.D.)--The University of Wisconsin - Madison, 2014.
506 $a This item must not be sold to any third party vendors.
520 $a Due to the failure of threshold voltage scaling, per-transistor switching power is not scaling down at the pace of Moore's Law, causing the power density to rise for each successive generation. Consequently, computer architects need to improve the energy efficiency of microarchitecture designs to sustain the traditional performance growth. Hardware specialization or using accelerators is a promising direction to improve the energy efficiency without sacrificing performance. However, it requires disruptive changes in hardware and software including the programming model, applications, and operating systems. Moreover, specialized accelerators cannot help with the general purpose computing. Going forward, we need a solution that avoids such disruptive changes and can accelerate or specialize even general purpose workloads.
520 $a This thesis develops a hardware/software co-designed solution called Dynamically Specialized Execution, which uses compiler assisted dynamic specialization to improve the energy efficiency without radical changes to microarchitecture, the ISA or the programming model. This dissertation first develops a decoupled access/execute coarse-grain reconfigurable architecture called DySER: Dynamically Specialized Execution Resources, which achieves energy efficiency by creating specialized hardware at runtime for hot code regions. DySER exposes a well defined interface and execution model, which makes it easier to integrate DySER with an existing core microarchitecture. To address the challenges of compiling for a specialized accelerator, this thesis develops a novel compiler intermediate representation called the Access/Execute Program Dependence Graph (AEPDG), which accurately models DySER and captures the spatio-temporal aspects of its execution. This thesis shows that using this representation, we can implement a compiler that generates highly optimized code for a coarse-grain reconfigurable architecture without manual intervention for programs written in the traditional programming model.
520 $a Detailed evaluation shows that automatic specialization of data parallel workloads with DySER provides a mean speedup of 3.8x with 60% energy reduction when compared to a 4-wide out-of-order processor. On irregular workloads, exemplified by SPECCPU, DySER provides on average speedup of 11% with 10% reduction in energy consumption. On a highly relevant application, database query processing, which has a mix of data parallel kernels and irregular kernels, DySER provides an 2.7x speedup over the 4-wide out-of-order processor.
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