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Greedy coordinate descent CMP multi-...

Choi, Inseok Stephen.

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Greedy coordinate descent CMP multi-level cache resizing.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Greedy coordinate descent CMP multi-level cache resizing./
作者:	Choi, Inseok Stephen.
面頁冊數:	183 p.
附註:	Source: Dissertation Abstracts International, Volume: 75-11(E), Section: B.
Contained By:	Dissertation Abstracts International75-11B(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3628610
ISBN:	9781321047608

Greedy coordinate descent CMP multi-level cache resizing.
Choi, Inseok Stephen.

Greedy coordinate descent CMP multi-level cache resizing. - 183 p.

Source: Dissertation Abstracts International, Volume: 75-11(E), Section: B.

Thesis (Ph.D.)--University of Maryland, College Park, 2014.

This item must not be sold to any third party vendors.

Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve better power efficiency. Cache resizing is a technique that can remove wasteful power consumption in caches. The idea is to determine the minimum cache a program needs to run at near-peak performance, and then reconfigure the cache to implement this efficient capacity. While there has been significant previous work on cache resizing, existing techniques have focused on controlling resizing for a single level of cache only. This sacrifices significant opportunities for power savings in modern CPU hierarchies which routinely employ 3 levels of cache. Moreover, as CMP scaling will likely continue for the foreseeable future, eliminating wasteful power consumption from a CMP multi-level cache hierarchy is crucial to achieve better power efficiency.

ISBN: 9781321047608Subjects--Topical Terms:

1669061
Engineering, Computer.

Greedy coordinate descent CMP multi-level cache resizing.
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245 1 0 $a Greedy coordinate descent CMP multi-level cache resizing.
300 $a 183 p.
500 $a Source: Dissertation Abstracts International, Volume: 75-11(E), Section: B.
500 $a Adviser: Donald Yeung.
502 $a Thesis (Ph.D.)--University of Maryland, College Park, 2014.
506 $a This item must not be sold to any third party vendors.
520 $a Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve better power efficiency. Cache resizing is a technique that can remove wasteful power consumption in caches. The idea is to determine the minimum cache a program needs to run at near-peak performance, and then reconfigure the cache to implement this efficient capacity. While there has been significant previous work on cache resizing, existing techniques have focused on controlling resizing for a single level of cache only. This sacrifices significant opportunities for power savings in modern CPU hierarchies which routinely employ 3 levels of cache. Moreover, as CMP scaling will likely continue for the foreseeable future, eliminating wasteful power consumption from a CMP multi-level cache hierarchy is crucial to achieve better power efficiency.
520 $a In this dissertation, we propose a noble technique, greedy coordinate descent CMP multi-level cache resizing, that minimizes a power consumption while maintaining a high performance. We simutaneously resizes all caches in a modern CMP cache hierarchy to minimize the power consumption. Specifically, our approach predicts the power consumption and the performance level without direct evaluations. We also develop greedy coordinate descent method to search an optimal cache configuration utilizing power efficiency gain (PEG) that we propose in this dissertation.
520 $a This dissertation makes three contributions for a CMP multi-level cache resizing. First, we discover the limits of power savings and performance. This limit study identifies the potential power savings in a CMP multi-level cache hierarchy when wasteful power consumption is eliminated. Second, we propose a prediction-based greedy coordinate descent (GCD) method to find an optimal cache configuration and to orchestrate them. Third, we implement online GCD techniques for a CMP multi-level cache resizing. Our approach exhibits 13.9% power savings and achieves 91% of the power savings of the static oracle cache hierarchy configuration.
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