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GPU and FPGA Coprocessors for Data I...

Honbo, Daniel.

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GPU and FPGA Coprocessors for Data Intensive Computations.

Record Type:	Electronic resources : Monograph/item
Title/Author:	GPU and FPGA Coprocessors for Data Intensive Computations./
Author:	Honbo, Daniel.
Description:	64 p.
Notes:	Source: Dissertation Abstracts International, Volume: 75-10(E), Section: B.
Contained By:	Dissertation Abstracts International75-10B(E).
Subject:	Engineering, Computer. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3626701
ISBN:	9781321017267

GPU and FPGA Coprocessors for Data Intensive Computations.
Honbo, Daniel.

GPU and FPGA Coprocessors for Data Intensive Computations. - 64 p.

Source: Dissertation Abstracts International, Volume: 75-10(E), Section: B.

Thesis (Ph.D.)--Northwestern University, 2014.

With the current norm of multi-core processors, stagnant clock rates, and slowing gains from instruction level parallelism, it has become increasingly important to exploit parallelism in order to achieve acceptable performance for data intensive tasks. While multi-core processors are fine for exploiting thread-level parallelism, they are often a suboptimal choice for problems that exhibit abundant data parallelism. This thesis investigates the application of Graphics Processing Units (GPUs) and Field Programmable Gate Array (FPGA) coprocessors for data intensive, data parallel workloads.

ISBN: 9781321017267Subjects--Topical Terms:

1669061
Engineering, Computer.

GPU and FPGA Coprocessors for Data Intensive Computations.
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245 1 0 $a GPU and FPGA Coprocessors for Data Intensive Computations.
300 $a 64 p.
500 $a Source: Dissertation Abstracts International, Volume: 75-10(E), Section: B.
500 $a Adviser: Alok Choudhary.
502 $a Thesis (Ph.D.)--Northwestern University, 2014.
520 $a With the current norm of multi-core processors, stagnant clock rates, and slowing gains from instruction level parallelism, it has become increasingly important to exploit parallelism in order to achieve acceptable performance for data intensive tasks. While multi-core processors are fine for exploiting thread-level parallelism, they are often a suboptimal choice for problems that exhibit abundant data parallelism. This thesis investigates the application of Graphics Processing Units (GPUs) and Field Programmable Gate Array (FPGA) coprocessors for data intensive, data parallel workloads.
520 $a Since adopting a unified shader architecture and a general programming model, GPUs have become an increasingly important alternative to general-purpose processors for compute intensive applications, since they feature peak floating-point performance well above that of general-purpose processors. We investigate GPU coprocessors for a simple particle simulation and demonstrate the performance benefit of offloading spatial transformations and basic particle motion calculations to a GPU. We also study a GPU coprocessor for the k-Means clustering algorithm and demonstrate application speedups of 40-70x.
520 $a FPGAs are hardware devices capable of implementing arbitrary digital circuits. The vast internal bandwidth and low power consumption afforded by these devices makes them an attractive target for certain data parallel workloads. We investigate FPGA architecture for Decision Tree Classification that can achieve a speedup of 30x for the split determination phase of the algorithm. We also present a fast pairwise statistical significance estimation architecture using an FPGA coprocessor that offloads the alignment task to an accelerator designed to concurrently process multiple independent alignments, resulting in an end-to-end speedup of over 200x over a baseline software implementation.
590 $a School code: 0163.
650 4 $a Engineering, Computer. $3 1669061
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710 2 $a Northwestern University. $b Electrical and Computer Engineering. $3 1022291
773 0 $t Dissertation Abstracts International $g 75-10B(E).
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791 $a Ph.D.
792 $a 2014
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