語系:
繁體中文
English
說明(常見問題)
回圖書館首頁
手機版館藏查詢
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Low power interconnect design
~
Saini, Sandeep.
FindBook
Google Book
Amazon
博客來
Low power interconnect design
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Low power interconnect design/ by Sandeep Saini.
作者:
Saini, Sandeep.
出版者:
New York, NY :Springer New York : : 2015.,
面頁冊數:
xvii, 152 p. :ill. (some col.), digital ;24 cm.
內容註:
Part I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
Contained By:
Springer eBooks
標題:
Interconnects (Integrated circuit technology) - Design. -
電子資源:
http://dx.doi.org/10.1007/978-1-4614-1323-3
ISBN:
9781461413233 (electronic bk.)
Low power interconnect design
Saini, Sandeep.
Low power interconnect design
[electronic resource] /by Sandeep Saini. - New York, NY :Springer New York :2015. - xvii, 152 p. :ill. (some col.), digital ;24 cm.
Part I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
ISBN: 9781461413233 (electronic bk.)
Standard No.: 10.1007/978-1-4614-1323-3doiSubjects--Topical Terms:
2131821
Interconnects (Integrated circuit technology)
--Design.
LC Class. No.: TK7874.53
Dewey Class. No.: 621.3815
Low power interconnect design
LDR
:01259nam a2200301 a 4500
001
2007637
003
DE-He213
005
20160120134612.0
006
m d
007
cr nn 008maaau
008
160219s2015 nyu s 0 eng d
020
$a
9781461413233 (electronic bk.)
020
$a
9781461413226 (paper)
024
7
$a
10.1007/978-1-4614-1323-3
$2
doi
035
$a
978-1-4614-1323-3
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
TK7874.53
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
082
0 4
$a
621.3815
$2
23
090
$a
TK7874.53
$b
.S132 2015
100
1
$a
Saini, Sandeep.
$3
2156552
245
1 0
$a
Low power interconnect design
$h
[electronic resource] /
$c
by Sandeep Saini.
260
$a
New York, NY :
$b
Springer New York :
$b
Imprint: Springer,
$c
2015.
300
$a
xvii, 152 p. :
$b
ill. (some col.), digital ;
$c
24 cm.
505
0
$a
Part I Basics of Interconnect Design -- Introduction to Interconnects -- CMOS Buffer -- Part II Buffer and Schmidt trigger Insertion Techniques for Low Power Interconnect Design -- Buffer Insertion as a Solution to Interconnect Issues -- Schmidt Trigger Approach -- Part III Bus Coding Techniques for Low Power Interconnect Design -- Bus Coding Techniques.
650
0
$a
Interconnects (Integrated circuit technology)
$x
Design.
$3
2131821
650
1 4
$a
Engineering.
$3
586835
650
2 4
$a
Circuits and Systems.
$3
896527
650
2 4
$a
Electronics and Microelectronics, Instrumentation.
$3
893838
650
2 4
$a
Processor Architectures.
$3
892680
710
2
$a
SpringerLink (Online service)
$3
836513
773
0
$t
Springer eBooks
856
4 0
$u
http://dx.doi.org/10.1007/978-1-4614-1323-3
950
$a
Engineering (Springer-11647)
筆 0 讀者評論
館藏地:
全部
電子資源
出版年:
卷號:
館藏
1 筆 • 頁數 1 •
1
條碼號
典藏地名稱
館藏流通類別
資料類型
索書號
使用類型
借閱狀態
預約狀態
備註欄
附件
W9273342
電子資源
11.線上閱覽_V
電子書
EB TK7874.53 .S132 2015
一般使用(Normal)
在架
0
1 筆 • 頁數 1 •
1
多媒體
評論
新增評論
分享你的心得
Export
取書館
處理中
...
變更密碼
登入