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SVA = The Power of Assertions in Sys...

Cerny, Eduard.

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SVA = The Power of Assertions in SystemVerilog /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	SVA/ by Eduard Cerny ... [et al.].
其他題名:	The Power of Assertions in SystemVerilog /
其他作者:	Cerny, Eduard.
出版者:	Cham :Springer International Publishing : : 2015.,
面頁冊數:	xix, 590 p. :ill., digital ;24 cm.
內容註:	Part I. Opening -- Introduction -- System Verilog Language Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference -- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification -- Formal Verification and Models -- Formal Semantics -- Part VI. Advanced Checkers -- Checkers in Formal Verification -- Checker Libraries -- Appendix -- References.
Contained By:	Springer eBooks
標題:	SystemVerilog (Computer hardware description language) -
電子資源:	http://dx.doi.org/10.1007/978-3-319-07139-8
ISBN:	9783319071398 (electronic bk.)

SVA = The Power of Assertions in SystemVerilog /
SVAThe Power of Assertions in SystemVerilog /[electronic resource] :by Eduard Cerny ... [et al.]. - 2nd ed. - Cham :Springer International Publishing :2015. - xix, 590 p. :ill., digital ;24 cm.

Part I. Opening -- Introduction -- System Verilog Language Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference -- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification -- Formal Verification and Models -- Formal Semantics -- Part VI. Advanced Checkers -- Checkers in Formal Verification -- Checker Libraries -- Appendix -- References.

This book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA) It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader SystemVerilog language, demonstrating the ways that assertions can interact with other SystemVerilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists, and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students. Provides a comprehensive guide to assertion-based verification with SystemVerilog Assertions (SVA); Includes step-by-step examples of how SVA can be used to construct powerful and reusable sets of properties. Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 SystemVerilog standard.

ISBN: 9783319071398 (electronic bk.)

Standard No.: 10.1007/978-3-319-07139-8doiSubjects--Topical Terms:

2132678
SystemVerilog (Computer hardware description language)

LC Class. No.: TK7885.7

Dewey Class. No.: 621.392

SVA = The Power of Assertions in SystemVerilog /
LDR:03408nmm a2200325 a 4500 001 1994060
003 DE-He213
005 20150520164028.0
006 m d
007 cr nn 008maaau
008 151019s2015 gw s 0 eng d
020 $a 9783319071398 (electronic bk.)
020 $a 9783319071381 (paper)
024 7 $a 10.1007/978-3-319-07139-8 $2 doi
035 $a 978-3-319-07139-8
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7885.7
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.392 $2 23
090 $a TK7885.7 $b .S968 2015
245 0 0 $a SVA $h [electronic resource] : $b The Power of Assertions in SystemVerilog / $c by Eduard Cerny ... [et al.].
250 $a 2nd ed.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2015.
300 $a xix, 590 p. : $b ill., digital ; $c 24 cm.
505 0 $a Part I. Opening -- Introduction -- System Verilog Language Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference -- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification -- Formal Verification and Models -- Formal Semantics -- Part VI. Advanced Checkers -- Checkers in Formal Verification -- Checker Libraries -- Appendix -- References.
520 $a This book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA) It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader SystemVerilog language, demonstrating the ways that assertions can interact with other SystemVerilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists, and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students. Provides a comprehensive guide to assertion-based verification with SystemVerilog Assertions (SVA); Includes step-by-step examples of how SVA can be used to construct powerful and reusable sets of properties. Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 SystemVerilog standard.
650 0 $a SystemVerilog (Computer hardware description language) $3 2132678
650 1 4 $a Engineering. $3 586835
650 2 4 $a Circuits and Systems. $3 896527
650 2 4 $a Processor Architectures. $3 892680
650 2 4 $a Electronic Circuits and Devices. $3 1245773
700 1 $a Cerny, Eduard. $3 1629098
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-07139-8
950 $a Engineering (Springer-11647)