Advanced hardware design for error c...
Chavet, Cyrille.

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  • Advanced hardware design for error correcting codes
  • 紀錄類型: 書目-電子資源 : Monograph/item
    正題名/作者: Advanced hardware design for error correcting codes/ edited by Cyrille Chavet, Philippe Coussy.
    其他作者: Chavet, Cyrille.
    出版者: Cham :Springer International Publishing : : 2015.,
    面頁冊數: ix,192 p. :ill. (some col.), digital ;24 cm.
    內容註: User Needs -- Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding -- Implementation of Polar Decoders -- Parallel architectures for Turbo Product Codes Decoding -- VLSI implementations of sphere detectors -- Stochastic Decoders for LDPC Codes -- MP-SoC/NoC architectures for error correction -- ASIP design for multi-standard channel decoders -- Hardware design of parallel interleaver architecture: a survey.
    Contained By: Springer eBooks
    標題: Error-correcting codes (Information theory) -
    電子資源: http://dx.doi.org/10.1007/978-3-319-10569-7
    ISBN: 9783319105697 (electronic bk.)
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