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Dynamic cache reconfiguration based ...

Mittal, Sparsh.

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Dynamic cache reconfiguration based techniques for improving cache energy efficiency.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Dynamic cache reconfiguration based techniques for improving cache energy efficiency./
作者:	Mittal, Sparsh.
面頁冊數:	142 p.
附註:	Source: Dissertation Abstracts International, Volume: 74-10(E), Section: B.
Contained By:	Dissertation Abstracts International74-10B(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3566111
ISBN:	9781303168840

Dynamic cache reconfiguration based techniques for improving cache energy efficiency.
Mittal, Sparsh.

Dynamic cache reconfiguration based techniques for improving cache energy efficiency. - 142 p.

Source: Dissertation Abstracts International, Volume: 74-10(E), Section: B.

Thesis (Ph.D.)--Iowa State University, 2013.

Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems.

ISBN: 9781303168840Subjects--Topical Terms:

1669061
Engineering, Computer.

Dynamic cache reconfiguration based techniques for improving cache energy efficiency.
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245 1 0 $a Dynamic cache reconfiguration based techniques for improving cache energy efficiency.
300 $a 142 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-10(E), Section: B.
500 $a Adviser: Zhao Zhang.
502 $a Thesis (Ph.D.)--Iowa State University, 2013.
520 $a Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems.
520 $a In this research, we propose novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. We propose software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with the state-of-art techniques and have found that our techniques outperform them in their energy efficiency. This research has important applications in improving energy-efficiency of higher-end embedded, desktop, server processors and multitasking systems. We have also proposed performance estimation approach for efficient design space exploration and have implemented time-sampling based simulation acceleration approach for full-system architectural simulators.
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