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Reducing energy consumption through ...

Shuaib, Muhammad.

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Reducing energy consumption through data migration analysis in embedded systems.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Reducing energy consumption through data migration analysis in embedded systems./
作者:	Shuaib, Muhammad.
面頁冊數:	58 p.
附註:	Source: Masters Abstracts International, Volume: 51-06.
Contained By:	Masters Abstracts International51-06(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1523000
ISBN:	9781303176982

Reducing energy consumption through data migration analysis in embedded systems.
Shuaib, Muhammad.

Reducing energy consumption through data migration analysis in embedded systems. - 58 p.

Source: Masters Abstracts International, Volume: 51-06.

Thesis (M.S.)--University of Houston-Clear Lake, 2013.

Since most of the energy is consumed by memory components in many embedded architectures running data-intensive (image/video processing and scientific computations) applications, many designers focus their attention on memory components when trying to optimize various metrics such as power/energy consumption, performance, heat, reliability, cost, etc. Typically these optimization metrics are closely related to each other; in other words, it may also be necessary to do some trade-offs to keep one of these targeting metrics under control. For example, some reasonable performance degradation may be allowed in order to keep the energy consumption under a given limit. There are many effective techniques, algorithms and approaches that have been investigated and improved by the scientists in order to reduce energy consumption. Banking is one of these effective methods and is achieved by dividing the available memory space into a number of portions (banks). Data is divided into small units called blocks and these blocks are mapped to these banks. Multi-bank memory structures are widely used in single/multi-core embedded systems as they have better performance and power/energy consumption values compared to their single monolithic counterparts. These structures are achieved by partitioning available memory space into multiple banks, then placing each of those banks into various operating modes from active mode (during used period) to power down mode (during idle period). Energy consumption as well as resynchronization costs (penalty) of these operating modes are different. Scientists need to be very careful to utilize these operating modes in their techniques because frequent transition in the states of banks can have adverse effects on energy consumption as well as on performance.

ISBN: 9781303176982Subjects--Topical Terms:

1669061
Engineering, Computer.

Reducing energy consumption through data migration analysis in embedded systems.
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245 1 0 $a Reducing energy consumption through data migration analysis in embedded systems.
300 $a 58 p.
500 $a Source: Masters Abstracts International, Volume: 51-06.
500 $a Adviser: Hakduran Koc.
502 $a Thesis (M.S.)--University of Houston-Clear Lake, 2013.
520 $a Since most of the energy is consumed by memory components in many embedded architectures running data-intensive (image/video processing and scientific computations) applications, many designers focus their attention on memory components when trying to optimize various metrics such as power/energy consumption, performance, heat, reliability, cost, etc. Typically these optimization metrics are closely related to each other; in other words, it may also be necessary to do some trade-offs to keep one of these targeting metrics under control. For example, some reasonable performance degradation may be allowed in order to keep the energy consumption under a given limit. There are many effective techniques, algorithms and approaches that have been investigated and improved by the scientists in order to reduce energy consumption. Banking is one of these effective methods and is achieved by dividing the available memory space into a number of portions (banks). Data is divided into small units called blocks and these blocks are mapped to these banks. Multi-bank memory structures are widely used in single/multi-core embedded systems as they have better performance and power/energy consumption values compared to their single monolithic counterparts. These structures are achieved by partitioning available memory space into multiple banks, then placing each of those banks into various operating modes from active mode (during used period) to power down mode (during idle period). Energy consumption as well as resynchronization costs (penalty) of these operating modes are different. Scientists need to be very careful to utilize these operating modes in their techniques because frequent transition in the states of banks can have adverse effects on energy consumption as well as on performance.
520 $a In our current research, we propose to utilize data migration technique in a single core embedded system with software-managed memory architecture. This embedded system has an on-chip as well as off-chip memory, where off-chip memory is composed of multiple banks including a small sized Migrate Bank. We employ data migration technique to place/keep banks in low power operating modes for a longer time. This technique migrates and maps consecutive accessed blocks to a particular small sized bank, called Migrate Bank, so that energy consumption could be reduced by decreasing the number of bigger sized active banks. The content of Migrate Bank changes dynamically as working sets (loops) of the application change during the course of execution. Experimental results observed by our approach show that our proposed data migration technique with Migrate Bank can reduce energy consumption significantly.
520 $a Our target architecture utilizes Scratch Pad Memories (SPMs) as well since they are known to have many advantages over hardware-controlled counterparts. Actually these memories are managed by software and their size is small, so these memories do not encounter the problem of unpredicted misses; in other words, there is no need to check if data is available in SPM or not. Thus, it brings elimination of comparator and tag bits resulting in fast access time, less power/energy consumption, reduced cost, and real-time predictability.
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