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Background digital calibration of SA...

Wang, Guanhua.

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Background digital calibration of SAR ADC with fast FPGA emulation.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Background digital calibration of SAR ADC with fast FPGA emulation./
作者:	Wang, Guanhua.
面頁冊數:	62 p.
附註:	Source: Masters Abstracts International, Volume: 52-02.
Contained By:	Masters Abstracts International52-02(E).
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1545570
ISBN:	9781303406454

Background digital calibration of SAR ADC with fast FPGA emulation.
Wang, Guanhua.

Background digital calibration of SAR ADC with fast FPGA emulation. - 62 p.

Source: Masters Abstracts International, Volume: 52-02.

Thesis (M.S.E.E.)--The University of Texas at Dallas, 2013.

This dissertation presents a background calibration technique of successive approximation register (SAR) analog-to-digital converter (ADC) and a FPGA emulation platform for fast verification. The bit-weight calibration of a sub-binary weighted SAR ADC is based on the internal redundancy dithering (IRD) technique. A coarse ADC is employed as the reference path to remove the input interference problem in correlation-based background calibration. A custom FPGA emulation platform is developed to verify the proposed calibration approach, which achieves a 3000 speedup for the same simulation executed on a general-purpose microprocessor. Emulation results show that the signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 56dB to 89dB and 64dB to 115dB, respectively, for a sub-binary-weighted 16-bit SAR ADC with 1% DAC mismatch errors.

ISBN: 9781303406454Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Background digital calibration of SAR ADC with fast FPGA emulation.
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245 1 0 $a Background digital calibration of SAR ADC with fast FPGA emulation.
300 $a 62 p.
500 $a Source: Masters Abstracts International, Volume: 52-02.
500 $a Adviser: Yun Chiu.
502 $a Thesis (M.S.E.E.)--The University of Texas at Dallas, 2013.
520 $a This dissertation presents a background calibration technique of successive approximation register (SAR) analog-to-digital converter (ADC) and a FPGA emulation platform for fast verification. The bit-weight calibration of a sub-binary weighted SAR ADC is based on the internal redundancy dithering (IRD) technique. A coarse ADC is employed as the reference path to remove the input interference problem in correlation-based background calibration. A custom FPGA emulation platform is developed to verify the proposed calibration approach, which achieves a 3000 speedup for the same simulation executed on a general-purpose microprocessor. Emulation results show that the signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 56dB to 89dB and 64dB to 115dB, respectively, for a sub-binary-weighted 16-bit SAR ADC with 1% DAC mismatch errors.
590 $a School code: 0382.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a The University of Texas at Dallas. $b Electrical Engineering. $3 1679269
773 0 $t Masters Abstracts International $g 52-02(E).
790 $a 0382
791 $a M.S.E.E.
792 $a 2013
793 $a English
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