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Design and Analysis of Minimum Energ...

Grossmann, Peter.

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Design and Analysis of Minimum Energy FPGAs.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Design and Analysis of Minimum Energy FPGAs./
作者:	Grossmann, Peter.
面頁冊數:	120 p.
附註:	Source: Dissertation Abstracts International, Volume: 74-08(E), Section: B.
Contained By:	Dissertation Abstracts International74-08B(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3559193
ISBN:	9781303041723

Design and Analysis of Minimum Energy FPGAs.
Grossmann, Peter.

Design and Analysis of Minimum Energy FPGAs. - 120 p.

Source: Dissertation Abstracts International, Volume: 74-08(E), Section: B.

Thesis (Ph.D.)--Northeastern University, 2013.

Embedded systems continue to become smaller, demand greater compute capability, and target deployment in more energy-starved environments. System power budgets of less than 1 mW are increasingly common, while standby power is brought as close to zero as possible. While field programmable gate arrays (FPGAs) have historically been used as compute engines in low power systems, they have not kept pace with application-specific integrated circuits (ASICs) and microprocessors in meeting the needs of these ultra low power systems. Research in both ASICs and microprocessors has extended voltage scaling into the subthreshold region of transistor operation, sacrificing performance in exchange for dramatic power savings. For some ultra low power systems such as wireless sensor networks and implantable biomedical devices, performing a computation with minimum energy consumption rather than within a certain time frame is the goal. It has been shown that to minimize energy for ASICs and microprocessors, subthreshold operation is typically required. For FPGAs, the answer remains largely unexplored---the first subthreshold FPGA has only recently been fabricated, and minimum energy operation of FPGAs has not been thoroughly studied.

ISBN: 9781303041723Subjects--Topical Terms:

1669061
Engineering, Computer.

Design and Analysis of Minimum Energy FPGAs.
LDR:03449nam a2200289 4500 001 1963434
005 20141003074049.5
008 150210s2013 ||||||||||||||||| ||eng d
020 $a 9781303041723
035 $a (MiAaPQ)AAI3559193
035 $a AAI3559193
040 $a MiAaPQ $c MiAaPQ
100 1 $a Grossmann, Peter. $3 2099684
245 1 0 $a Design and Analysis of Minimum Energy FPGAs.
300 $a 120 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-08(E), Section: B.
500 $a Advisers: Miriam E. Leeser; Marvin Onabajo.
502 $a Thesis (Ph.D.)--Northeastern University, 2013.
520 $a Embedded systems continue to become smaller, demand greater compute capability, and target deployment in more energy-starved environments. System power budgets of less than 1 mW are increasingly common, while standby power is brought as close to zero as possible. While field programmable gate arrays (FPGAs) have historically been used as compute engines in low power systems, they have not kept pace with application-specific integrated circuits (ASICs) and microprocessors in meeting the needs of these ultra low power systems. Research in both ASICs and microprocessors has extended voltage scaling into the subthreshold region of transistor operation, sacrificing performance in exchange for dramatic power savings. For some ultra low power systems such as wireless sensor networks and implantable biomedical devices, performing a computation with minimum energy consumption rather than within a certain time frame is the goal. It has been shown that to minimize energy for ASICs and microprocessors, subthreshold operation is typically required. For FPGAs, the answer remains largely unexplored---the first subthreshold FPGA has only recently been fabricated, and minimum energy operation of FPGAs has not been thoroughly studied.
520 $a This research presents multiple steps forward in the design and analysis of FPGAs targeting minimum energy operation. A fabricated FPGA test chip capable of single-supply subthreshold operation is presented, with measurement results demonstrating FPGA programming and operation as low as 260 mV. The capability to minimize energy per clock cycle at subthreshold supply voltages for a high activity factor test case is also shown, indicating that the flexible nature of FPGAs does not inherently prevent their energy minimum occuring below threshold. A simulation flow for performing pre-fabrication chip-level minimum energy analysis for FPGAs has also been developed in this work. By combining industry-standard integrated circuit design verification software with academic FPGA software and custom scripts, the minimum energy point sensivity of an FPGA to its programming was investigated. The FPGA was programmed with 21 different ISCAS '85 benchmarks, and a minimum energy supply voltage was estimated for each with a nominal input activity factor. The benchmarks had minimum energy points ranging from 0.42-0.54 V, or slightly above threshold. The minimum energy point was not a strong function of benchmark circuit size or input count, suggesting that the topology of the benchmark circuit influenced the FPGA minimum energy point.
590 $a School code: 0160.
650 4 $a Engineering, Computer. $3 1669061
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0464
690 $a 0544
710 2 $a Northeastern University. $b Electrical and Computer Engineering. $3 1018491
773 0 $t Dissertation Abstracts International $g 74-08B(E).
790 $a 0160
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3559193