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Management and optimization for non-...

Hu, Jingtong.

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Management and optimization for non-volatile memories in embedded systems.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Management and optimization for non-volatile memories in embedded systems./
作者:	Hu, Jingtong.
面頁冊數:	183 p.
附註:	Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.
Contained By:	Dissertation Abstracts International74-12B(E).
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3592192
ISBN:	9781303331695

Management and optimization for non-volatile memories in embedded systems.
Hu, Jingtong.

Management and optimization for non-volatile memories in embedded systems. - 183 p.

Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.

Thesis (Ph.D.)--The University of Texas at Dallas, 2013.

Embedded systems are almost everywhere in our daily life nowadays. The proliferation of embedded systems has been accompanied by many technical challenges that are different from those faced by general-purpose computer systems. It is always desirable for embedded systems to have better performance, smaller size, and lower power consumption due to the size and power supply constraints. Memory is one of the most important subsystems that needs optimization since memory directly affects the system performance, occupies large die area, and consumes a large portion of system energy. This dissertation presents novel memory architectures for embedded systems with non-volatile memories (NVM) and proposed management and optimization techniques, including task scheduling, write reduction, and data allocation, for the NVM-based novel embedded system memory architectures.

ISBN: 9781303331695Subjects--Topical Terms:

626642
Computer Science.

Management and optimization for non-volatile memories in embedded systems.
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245 1 0 $a Management and optimization for non-volatile memories in embedded systems.
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500 $a Adviser: Edwin Sha.
502 $a Thesis (Ph.D.)--The University of Texas at Dallas, 2013.
520 $a Embedded systems are almost everywhere in our daily life nowadays. The proliferation of embedded systems has been accompanied by many technical challenges that are different from those faced by general-purpose computer systems. It is always desirable for embedded systems to have better performance, smaller size, and lower power consumption due to the size and power supply constraints. Memory is one of the most important subsystems that needs optimization since memory directly affects the system performance, occupies large die area, and consumes a large portion of system energy. This dissertation presents novel memory architectures for embedded systems with non-volatile memories (NVM) and proposed management and optimization techniques, including task scheduling, write reduction, and data allocation, for the NVM-based novel embedded system memory architectures.
520 $a Non-volatile memories, such as flash memory, Phase Change Memory (PCM), and Magnetic Random Access Memory (MRAM), have many desirable characteristics for embedded systems to employ them as main memory. These characteristics include low-cost, shock-resistivity, non-volatility, power-economy and high density. However, there are two common challenges we need to answer. First, non-volatile memory has limited write/erase cycles compared to DRAM. Second, a write operation is slower than a read operation on non-volatile memory. These two challenges can be answered by reducing the number of write activities on non-volatile main memory. For single-core embedded systems, we propose write-aware scheduling and recomputation, to minimize write activities on non-volatile memory. For multi-core embedded systems that employ NVM as their main memory, we introduce scheduling, data migration, and recomputation techniques to achieve the same goal. With the proposed techniques, the lifetime of NVM can be greatly extended and the memory access cost can be greatly reduced.
520 $a On-chip cache typically consumes 25%-50% of the processor's area and energy consumption, Scratch Pad Memory (SPM), a software-controlled on-chip memory, has been widely adopted in many embedded systems due to SPM's smaller area and lower power consumption. However, leakage power consumption is becoming a critical issue for SPM in embedded system. To address this problem, we propose a novel hybrid SPM (HSPM) which consists of SRAM and NVM to take advantage of the ultra-low leakage power and high density of NVM. Novel dynamic data management algorithms are proposed to make use of the full potential of NVM for both single-core and multi-core processors. The proposed novel HSPM with the new data management algorithm can greatly reduce the memory access time, dynamic energy and leakage power consumption.
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