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Wireless neural recording and stimul...
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Abdelhalim, Karim.
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Wireless neural recording and stimulation SoCs for monitoring and treatment of intractable epilepsy.
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Wireless neural recording and stimulation SoCs for monitoring and treatment of intractable epilepsy./
作者:
Abdelhalim, Karim.
面頁冊數:
243 p.
附註:
Source: Dissertation Abstracts International, Volume: 75-05(E), Section: B.
Contained By:
Dissertation Abstracts International75-05B(E).
標題:
Engineering, Computer. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=NS22004
ISBN:
9780499220042
Wireless neural recording and stimulation SoCs for monitoring and treatment of intractable epilepsy.
Abdelhalim, Karim.
Wireless neural recording and stimulation SoCs for monitoring and treatment of intractable epilepsy.
- 243 p.
Source: Dissertation Abstracts International, Volume: 75-05(E), Section: B.
Thesis (Ph.D.)--University of Toronto (Canada), 2013.
This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy.
ISBN: 9780499220042Subjects--Topical Terms:
1669061
Engineering, Computer.
Wireless neural recording and stimulation SoCs for monitoring and treatment of intractable epilepsy.
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This dissertation presents the system architecture and implementation of two wireless systems-on-chip (SoCs) for diagnostics and treatment of neurological disorders. It also validates the SoCs as an electronic implant for preoperative monitoring and treatment of intractable epilepsy.
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The first prototype SoC is a neural recording interface intended for wireless monitoring of intractable epilepsy. The 0.13microm CMOS SoC has 64 recording channels, 64 programmable FIR filters and an integrated 915MHz FSK PLL-based wireless transmitter. Each channel contains a low-noise amplifier and a modified 8-bit SAR ADC that and can provide analog-digital multiplication by modifying the ADC sampling phase. It is used in conjunction with 12-bit digital adders and registers to implement 64 16-tap FIR filters with a minimal area and power overhead. In vivo measurement results from freely moving rodents demonstrate its utility in preoperative monitoring epileptic seizures.
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Treatment of intractable epilepsy by responsive neurostimulation requires seizure detection capabilities. Next, a low-power VLSI processor architecture for early seizure detection is described. It the magnitude, phase and phase synchronization of two neural signals---all precursors of a seizure. The processor is utilized in an implantable responsive neural stimulator application. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The efficacy of the processor in epileptic seizure detection is validated on human EEG data and yields comparable performance to software-based algorithms.
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The second prototype SoC is a closed-loop 64-channel neural stimulator that includes the aforementioned seizure detector processor and is used for preventive seizure abortion. It constitutes a neural vector analyzer that monitors the magnitude, phase and phase synchronization of neural signals to enable seizure detection. In a closed loop, abnormal phase synchrony triggers the programmable-waveform biphasic neural stimulator. To implement these functionalities, the 0.13microm CMOS SoC integrates 64 amplifiers with switched-capacitor (SC) bandpass filters, 64 MADCs, 64 16-tap FIR filters, a processor, 64 biphasic stimulators and a wireless transmitter. The SoC is validated in the detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. The results demonstrate its utility in treatment of intractable epilepsy.
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