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Electro-thermal codesign in liquid c...

Shi, Bing.

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Electro-thermal codesign in liquid cooled 3D ICs: Pushing the power-performance limits.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Electro-thermal codesign in liquid cooled 3D ICs: Pushing the power-performance limits./
作者:	Shi, Bing.
面頁冊數:	161 p.
附註:	Source: Dissertation Abstracts International, Volume: 75-02(E), Section: B.
Contained By:	Dissertation Abstracts International75-02B(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3600049
ISBN:	9781303499654

Electro-thermal codesign in liquid cooled 3D ICs: Pushing the power-performance limits.
Shi, Bing.

Electro-thermal codesign in liquid cooled 3D ICs: Pushing the power-performance limits. - 161 p.

Source: Dissertation Abstracts International, Volume: 75-02(E), Section: B.

Thesis (Ph.D.)--University of Maryland, College Park, 2013.

The performance improvement of today's computer systems is usually accompanied by increased chip power consumption and system temperature. Modern CPUs dissipate an average of 70-100W power while spatial and temporal power variations result in hotspots with even higher power density (up to 300W/cm.

ISBN: 9781303499654Subjects--Topical Terms:

1669061
Engineering, Computer.

Electro-thermal codesign in liquid cooled 3D ICs: Pushing the power-performance limits.
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245 1 0 $a Electro-thermal codesign in liquid cooled 3D ICs: Pushing the power-performance limits.
300 $a 161 p.
500 $a Source: Dissertation Abstracts International, Volume: 75-02(E), Section: B.
500 $a Adviser: Ankur Srivastava.
502 $a Thesis (Ph.D.)--University of Maryland, College Park, 2013.
520 $a The performance improvement of today's computer systems is usually accompanied by increased chip power consumption and system temperature. Modern CPUs dissipate an average of 70-100W power while spatial and temporal power variations result in hotspots with even higher power density (up to 300W/cm.
520 $a 2). The coming years will continue to witness a significant increasein CPU power dissipation due to advanced multi-core architectures and 3D integration technologies. Nowadays the problems of increased chip power density, leakage power and system temperatures have become major obstacles for further improvement in chip performance. The conventional air cooling based heat sink has been proved to be insufficient for three dimensional integrated circuits (3D-ICs). Hence better cooling solutions are necessary. Micro-fluidic cooling, which integrates micro-channel heat sinks into silicon substrates of the chip and uses liquid flow to remove heat inside the chip, is an effective active cooling scheme for 3D-ICs. While the micro-fluidic cooling provides excellent cooling to 3D-ICs, the associated overhead (cooling power consumed by the pump to inject the coolant through micro-channels) is significant. Moreover, the 3D-IC structure also imposes constraints on micro-channel locations (basically resource conflict with through-silicon-vias TSVs or other structures).
520 $a In this work, we investigate optimized micro-channel configurations that address the aforementioned considerations. We develop three micro-channel structures (hotspot optimized cooling configuration, bended micro-channel and hybrid cooling network) that can provide sufficient cooling to 3D-IC with minimum cooling power overhead, while at the same time, compatible with the existing electrical structure such as TSVs. These configurations can achieve up to 70% cooling power savings compared with the configuration without any optimization. Based on these configurations, we then develop a micro-fluidic cooling based dynamic thermal management approach that maintains the chip temperature through controlling the fluid flow rate (pressure drop) through micro-channels. These cooling configurations are designed after the electrical parts, and therefore, compatible with the current standard IC design flow.
520 $a Furthermore, the electrical, thermal, cooling and mechanical aspects of 3D-IC are interdependent. Hence the conventional design flow that designs the cooling configuration after electrical aspect is finished will result in inefficiencies. In order to overcome this problem, we then investigate electrical-thermal co-design methodology for 3D-ICs. Two co-design problems are explored: TSV assignment and micro-channel placement co-design, and gate sizing and fluidic cooling co-design. The experimental results show that the co-design enables a fundamental power-performance improvement over the conventional design flow which separates the electrical and cooling design. For example, the gate sizing and fluidic cooling co-design achieves 12% power savings under the same circuit timing constraint and 16% circuit speedup under the same power budget.
590 $a School code: 0117.
650 4 $a Engineering, Computer. $3 1669061
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Engineering, Mechanical. $3 783786
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710 2 $a University of Maryland, College Park. $b Electrical Engineering. $3 1018746
773 0 $t Dissertation Abstracts International $g 75-02B(E).
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791 $a Ph.D.
792 $a 2013
793 $a English
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