東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

3D Stacked Memories for Digital Sign...

Chang, Daniel W.

Linked to FindBook

Google Book

Amazon

博客來

3D Stacked Memories for Digital Signal Processors.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	3D Stacked Memories for Digital Signal Processors./
Author:	Chang, Daniel W.
Description:	107 p.
Notes:	Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.
Contained By:	Dissertation Abstracts International74-12B(E).
Subject:	Engineering, Computer. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3589964
ISBN:	9781303291494

3D Stacked Memories for Digital Signal Processors.
Chang, Daniel W.

3D Stacked Memories for Digital Signal Processors. - 107 p.

Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.

Thesis (Ph.D.)--The University of Wisconsin - Madison, 2013.

Recently, three-dimensional (3D) integration technology has enabled researchers to explore novel architectures. Due to the growing memory requirements of modern signal processing applications, it was thought that digital signal processors (DSPs) could benefit from 3D memory integration technology where high-density memories are placed below processing cores. Until recently, it was believed that this integration could lower memory latencies by 45% to 60%, which would improve performance. 3D memory integration technology also allowed a large increase in the main memory bus width by using small through silicon vias (TSVs) instead of off-chip metal wires. This increase in the bus width meant each main memory request could bring more data into the last-level on-chip memory and improve the performance of streaming applications whose memory access behavior exhibits a large amount of spatial locality.

ISBN: 9781303291494Subjects--Topical Terms:

1669061
Engineering, Computer.

3D Stacked Memories for Digital Signal Processors.
LDR:03154nam a2200301 4500 001 1960333
005 20140611111837.5
008 150210s2013 ||||||||||||||||| ||eng d
020 $a 9781303291494
035 $a (MiAaPQ)AAI3589964
035 $a AAI3589964
040 $a MiAaPQ $c MiAaPQ
100 1 $a Chang, Daniel W. $3 2095967
245 1 0 $a 3D Stacked Memories for Digital Signal Processors.
300 $a 107 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-12(E), Section: B.
500 $a Adviser: Michael J. Schulte.
502 $a Thesis (Ph.D.)--The University of Wisconsin - Madison, 2013.
520 $a Recently, three-dimensional (3D) integration technology has enabled researchers to explore novel architectures. Due to the growing memory requirements of modern signal processing applications, it was thought that digital signal processors (DSPs) could benefit from 3D memory integration technology where high-density memories are placed below processing cores. Until recently, it was believed that this integration could lower memory latencies by 45% to 60%, which would improve performance. 3D memory integration technology also allowed a large increase in the main memory bus width by using small through silicon vias (TSVs) instead of off-chip metal wires. This increase in the bus width meant each main memory request could bring more data into the last-level on-chip memory and improve the performance of streaming applications whose memory access behavior exhibits a large amount of spatial locality.
520 $a My dissertation provides a more accurate 3D main memory model that demonstrates that the latency reduction of going from conventional DDR2 DRAM to 3D memory technology is roughly 4% instead of the often quoted 45% to 60%. With this model, I re-evaluate the performance impact of 3D main memory on DSPs and find the benefits from the latency savings are small.
520 $a I next analyze current 3D main memory with Wide I/O, which can lower main memory latencies by 15.9% and greatly increase the main memory bus width. I demonstrate that using 3D main memory with Wide I/O and increasing the main memory bus width from 64 bits to 4,096 bits can improve the average performance of signal processing applications by 9.7%, but also increases average energy consumption by 2.6%. For energy-constraint DSPs that are often found in mobile devices, this increase may be unacceptable.
520 $a To mitigate this energy increase, I propose novel techniques to dynamically scale the main memory bus width of a DSP based on the program phases of an application. These bandwidth scaling algorithms increase the main memory bus width during memory intense phases to improve performance and lower the bus width during compute intensive phases to improve energy efficiency. These algorithms can improve average DSP performance by 6.6% while increasing average energy consumption by only 0.5%.
590 $a School code: 0262.
650 4 $a Engineering, Computer. $3 1669061
690 $a 0464
710 2 $a The University of Wisconsin - Madison. $b Electrical Engineering. $3 2095968
773 0 $t Dissertation Abstracts International $g 74-12B(E).
790 $a 0262
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3589964