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Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service./
作者:	Tran, Le-Nguyen.
面頁冊數:	130 p.
附註:	Source: Dissertation Abstracts International, Volume: 74-05(E), Section: B.
Contained By:	Dissertation Abstracts International74-05B(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3548694
ISBN:	9781267843661

Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service.
Tran, Le-Nguyen.

Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service. - 130 p.

Source: Dissertation Abstracts International, Volume: 74-05(E), Section: B.

Thesis (Ph.D.)--University of California, Irvine, 2013.

In this dissertation, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for Dynamic Random Access Memory (DRAM) and 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduce power con- sumption. The DRAM/eDRAM is usually designed to sustain the worst operating conditions, and the chip is very rarely operated under these conditions. We exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicate that power consumption can be saved more than 10 times when the chip is normally operated. This keeps the chip cool and the operating temperature will be well under control, which helps in averting device degradation and ultimate breakdown. In addition, it is possible to extend the eDRAM data retention time, which helps to improve the memory availability and system performance. Then a mixed-signal controller that implements our algorithm is presented in detail. Our proposed control circuit dynamically adjusts the supply voltages and the refresh cycle with an awareness of process variations, temperature changes, and device degradation to reduce power consumption or enhance memory availability. We use the Predictive Technology Model(PTM) 45nm to design and simulate the controller. The silicon area of the controller is only 0.052 mm2 which is equivalent to the area of a 1.5 Megabit memory array. It operates at 100 MHz frequency and consumes about 260microW. Compared to a circuit which is designed to accommodate the worst case scenario, we can save power consumption or extend the memory availability more than ten times when our chip operates under normal conditions. After that an innovative memory management approach which utilize both 3D-DRAM and external DRAM (ex-DRAM) is presented. Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for "latency sensitive", "bandwidth sensitive", and "insensitive" applications. To improve the performance and satisfy a certain level of QoS, memory blocks of distinct application types are allocated differently. Compared to the scratchpad memory management mechanism, the average memory access latency of our approach decreases by 19% and 23%, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover, using our approach, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead, particularly for applications which have high spatial memory locality. Finally, we present a power-saving method for 3D-DRAM with an awareness of memory access workload variations. We dynamically and independently adjust supply voltages and refresh cycles of different 3D-DRAM dies to reduce their power consumption in the active and idle states. In fact, the same power saving method for DRAM/eDRAM, which exploits the design slack due to process variations and temperature changes, is applied for 3D-DRAM. In both states, we can still read/write normally and our method does not cause any performance overhead. The difference between these two states is the mechanism to reduce the power consumption: read/write operations and refresh operations consume the most power in the active and the idle state respectively. In addition, we implement a memory relocation mechanism so that recently accessed memory blocks are gathered together into common 3D-DRAM dies. That allows the others to be in the idle state to save power consumption. The memory relocation mechanism is also an extension of the proposed heterogeneous memory management approach. The overhead of our memory relocation mechanism is negligible. Our simulation shows that if there is no memory access (all 3D-DRAM dies change into the idle state) our method can save power consumption up to 75%. If the memory access workload is low, our method can save power consumption by almost 50%.

ISBN: 9781267843661Subjects--Topical Terms:

1669061
Engineering, Computer.

Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service.
LDR:05617nam a2200265 4500 001 1960320
005 20140611111834.5
008 150210s2013 ||||||||||||||||| ||eng d
020 $a 9781267843661
035 $a (MiAaPQ)AAI3548694
035 $a AAI3548694
040 $a MiAaPQ $c MiAaPQ
100 1 $a Tran, Le-Nguyen. $3 2095950
245 1 0 $a Power-saving method for DRAM/eDRAM and 3D-DRAM exploiting the process variations, temperature changes, device degradation, and memory access workload variations and innovative heterogeneous memory management approach using 3D-DRAM with Quality of Service.
300 $a 130 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-05(E), Section: B.
500 $a Adviser: Fadi Kurdahi.
502 $a Thesis (Ph.D.)--University of California, Irvine, 2013.
520 $a In this dissertation, we have devised an innovative approach to dynamically set supply voltages and refresh cycle for Dynamic Random Access Memory (DRAM) and 1T1C embedded Dynamic Random Access Memory (eDRAM). The approach helps us to reduce power con- sumption. The DRAM/eDRAM is usually designed to sustain the worst operating conditions, and the chip is very rarely operated under these conditions. We exploit the design slack while operating under more favorable conditions to power consumptions. Simulation results indicate that power consumption can be saved more than 10 times when the chip is normally operated. This keeps the chip cool and the operating temperature will be well under control, which helps in averting device degradation and ultimate breakdown. In addition, it is possible to extend the eDRAM data retention time, which helps to improve the memory availability and system performance. Then a mixed-signal controller that implements our algorithm is presented in detail. Our proposed control circuit dynamically adjusts the supply voltages and the refresh cycle with an awareness of process variations, temperature changes, and device degradation to reduce power consumption or enhance memory availability. We use the Predictive Technology Model(PTM) 45nm to design and simulate the controller. The silicon area of the controller is only 0.052 mm2 which is equivalent to the area of a 1.5 Megabit memory array. It operates at 100 MHz frequency and consumes about 260microW. Compared to a circuit which is designed to accommodate the worst case scenario, we can save power consumption or extend the memory availability more than ten times when our chip operates under normal conditions. After that an innovative memory management approach which utilize both 3D-DRAM and external DRAM (ex-DRAM) is presented. Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for "latency sensitive", "bandwidth sensitive", and "insensitive" applications. To improve the performance and satisfy a certain level of QoS, memory blocks of distinct application types are allocated differently. Compared to the scratchpad memory management mechanism, the average memory access latency of our approach decreases by 19% and 23%, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover, using our approach, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead, particularly for applications which have high spatial memory locality. Finally, we present a power-saving method for 3D-DRAM with an awareness of memory access workload variations. We dynamically and independently adjust supply voltages and refresh cycles of different 3D-DRAM dies to reduce their power consumption in the active and idle states. In fact, the same power saving method for DRAM/eDRAM, which exploits the design slack due to process variations and temperature changes, is applied for 3D-DRAM. In both states, we can still read/write normally and our method does not cause any performance overhead. The difference between these two states is the mechanism to reduce the power consumption: read/write operations and refresh operations consume the most power in the active and the idle state respectively. In addition, we implement a memory relocation mechanism so that recently accessed memory blocks are gathered together into common 3D-DRAM dies. That allows the others to be in the idle state to save power consumption. The memory relocation mechanism is also an extension of the proposed heterogeneous memory management approach. The overhead of our memory relocation mechanism is negligible. Our simulation shows that if there is no memory access (all 3D-DRAM dies change into the idle state) our method can save power consumption up to 75%. If the memory access workload is low, our method can save power consumption by almost 50%.
590 $a School code: 0030.
650 4 $a Engineering, Computer. $3 1669061
690 $a 0464
710 2 $a University of California, Irvine. $b Electrical and Computer Engineering - Ph.D.. $3 2094166
773 0 $t Dissertation Abstracts International $g 74-05B(E).
790 $a 0030
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3548694