東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Robust Design Techniques for Emergin...

Zamani, Masoud.

FindBook

Google Book

Amazon

博客來

Robust Design Techniques for Emerging Technologies of Computing.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Robust Design Techniques for Emerging Technologies of Computing./
作者:	Zamani, Masoud.
面頁冊數:	110 p.
附註:	Source: Dissertation Abstracts International, Volume: 74-08(E), Section: B.
Contained By:	Dissertation Abstracts International74-08B(E).
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3559212
ISBN:	9781303041969

Robust Design Techniques for Emerging Technologies of Computing.
Zamani, Masoud.

Robust Design Techniques for Emerging Technologies of Computing. - 110 p.

Source: Dissertation Abstracts International, Volume: 74-08(E), Section: B.

Thesis (Ph.D.)--Northeastern University, 2013.

Conventional CMOS technology used in implementation of computational circuits faces major challenges in continues downscaling. Therefore, researchers explore alternative emerging implementation technologies and alternative computational approaches to overcome these challenges. However, in nanoscale regimes due to atomic scale of devices and poor control in nanofabrication, reliability is a major challenge. In this thesis, we will study reliability issues in crossbar nano-architectures, as an example of alternative implementation, as well as reversible logic, as an example of alternative computational technology.

ISBN: 9781303041969Subjects--Topical Terms:

1669061
Engineering, Computer.

Robust Design Techniques for Emerging Technologies of Computing.
LDR:03274nam a2200301 4500 001 1959339
005 20140520124006.5
008 150210s2013 ||||||||||||||||| ||eng d
020 $a 9781303041969
035 $a (MiAaPQ)AAI3559212
035 $a AAI3559212
040 $a MiAaPQ $c MiAaPQ
100 1 $a Zamani, Masoud. $3 2094734
245 1 0 $a Robust Design Techniques for Emerging Technologies of Computing.
300 $a 110 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-08(E), Section: B.
500 $a Adviser: Mehdi B. Tahoori.
502 $a Thesis (Ph.D.)--Northeastern University, 2013.
520 $a Conventional CMOS technology used in implementation of computational circuits faces major challenges in continues downscaling. Therefore, researchers explore alternative emerging implementation technologies and alternative computational approaches to overcome these challenges. However, in nanoscale regimes due to atomic scale of devices and poor control in nanofabrication, reliability is a major challenge. In this thesis, we will study reliability issues in crossbar nano-architectures, as an example of alternative implementation, as well as reversible logic, as an example of alternative computational technology.
520 $a We study two approaches, namely logic mapping and architectural techniques, to incorporate variation and defect tolerance in crossbar nano-architectures. In the logic mapping approach, different configurations of a logic function on a crossbar nano-architecture are explored to find a reliable configuration which results in better variation and defect tolerance. Simulation results, on a set of benchmarks circuits, show that the proposed method achieve variation tolerance more than 98% of the cases, while in 100% of the cases all defects are eliminated in the mapping. We also use asynchronous design methodologies to propose a self-time crossbar nano-architecture, which allows us to eliminate global clock-like signals (by replacing with local handshake signals) to reduce circuit vulnerability to delay variation. Compared to synchronous counterparts, with around 50% overhead the proposed architecture provides 100% tolerance to delay variations.
520 $a In terms of reversible circuits, we study online and offline testing of these circuits as well as fault masking and diagnosis. In order to provide online testing, we use a parity generation methodology to detect faults. This method provides 100% coverage for single fault and more than 99% coverage for multiple faults with 25% fault rate. Furthermore, a cyclic test generation methodology is used to provide test patterns with small amount of test information, applicable for in the field testing. We also propose a set of majority voting gates which can be used in Triple Modular Redundancy (TMR) circuits to enable both fault masking and fault diagnosis. Simulation results show that the average overhead of the proposed majority voters are less than 38% while they provide fault masking and diagnosis.
590 $a School code: 0160.
650 4 $a Engineering, Computer. $3 1669061
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0464
690 $a 0544
710 2 $a Northeastern University. $b Electrical and Computer Engineering. $3 1018491
773 0 $t Dissertation Abstracts International $g 74-08B(E).
790 $a 0160
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3559212