東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Development of improved methodology ...

Lee, Jui-Chu.

FindBook

Google Book

Amazon

博客來

Development of improved methodology for characterization and simulation of electrostatic discharge (ESD) in MOS devices and ICs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Development of improved methodology for characterization and simulation of electrostatic discharge (ESD) in MOS devices and ICs./
作者:	Lee, Jui-Chu.
面頁冊數:	123 p.
附註:	Source: Dissertation Abstracts International, Volume: 61-07, Section: B, page: 3757.
Contained By:	Dissertation Abstracts International61-07B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=9977817
ISBN:	0599837934

Development of improved methodology for characterization and simulation of electrostatic discharge (ESD) in MOS devices and ICs.
Lee, Jui-Chu.

Development of improved methodology for characterization and simulation of electrostatic discharge (ESD) in MOS devices and ICs. - 123 p.

Source: Dissertation Abstracts International, Volume: 61-07, Section: B, page: 3757.

Thesis (Ph.D.)--University of Central Florida, 2000.

This research first gives an overview of the ESD sources, models and permanent failure mechanism. Variable protection circuits are examined to look at ways of preventing ICs from being damaged should ESD events occur. Then this work has been segmented into two main parts. The first pertains to improving the methodology for ESD measurement. In particular, we provide simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the ESD HBM stress. Based on this mechanism, the correct pulse which is capable of producing results equivalent to the HBM test method using the transmission line pulse (TLP) technique is determined and recommended.

ISBN: 0599837934Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Development of improved methodology for characterization and simulation of electrostatic discharge (ESD) in MOS devices and ICs.
LDR:03160nmm 2200313 4500 001 1861175
005 20041111103133.5
008 130614s2000 eng d
020 $a 0599837934
035 $a (UnM)AAI9977817
035 $a AAI9977817
040 $a UnM $c UnM
100 1 $a Lee, Jui-Chu. $3 1948786
245 1 0 $a Development of improved methodology for characterization and simulation of electrostatic discharge (ESD) in MOS devices and ICs.
300 $a 123 p.
500 $a Source: Dissertation Abstracts International, Volume: 61-07, Section: B, page: 3757.
500 $a Major Professor: Juin J. Liou.
502 $a Thesis (Ph.D.)--University of Central Florida, 2000.
520 $a This research first gives an overview of the ESD sources, models and permanent failure mechanism. Variable protection circuits are examined to look at ways of preventing ICs from being damaged should ESD events occur. Then this work has been segmented into two main parts. The first pertains to improving the methodology for ESD measurement. In particular, we provide simulation and experimental results to determine the main mechanism governing the failure of MOS devices subjected to the ESD HBM stress. Based on this mechanism, the correct pulse which is capable of producing results equivalent to the HBM test method using the transmission line pulse (TLP) technique is determined and recommended.
520 $a This portion of the research also includes an improved experimental setup for ESD measurements based upon using TLP technique. The pulse waveforms generated by a traditional TLP setup, however, are often distorted by signal reflections. A new and simple experimental setup is developed to improve the shape of TLP waveforms and deliver higher current to the device under test (DUT). Experimental results obtained from the traditional and improved setups are presented and compared.
520 $a The final portion of this research is related to the development of an enhanced SPICE model for NMOS devices that have experienced HBM ESD events. Most semiconductor manufacturing companies use in-house developed circuit-level simulation tools to model ESD effects with limited success. This research attempts to create models compatible with the industry standard SPICE software tools to more accurately perform the simulation at the transistor level. For the most part SPICE tools are widely used by and available to integrated circuit design engineers. Model equations for N-channel MOS under the influence of ESD are derived based upon device physics and include parasitic bipolar action. A simple, but effective method for the extraction of parameters is presented. An approach to constructing the improved model in SPICE is also embraced in this research. Finally, comparisons of the DC and transient responses obtained from SPICE simulations and measurements are given.
590 $a School code: 0705.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Physics, Electricity and Magnetism. $3 1019535
650 4 $a Engineering, Materials Science. $3 1017759
690 $a 0544
690 $a 0607
690 $a 0794
710 2 0 $a University of Central Florida. $3 1018467
773 0 $t Dissertation Abstracts International $g 61-07B.
790 1 0 $a Liou, Juin J., $e advisor
790 $a 0705
791 $a Ph.D.
792 $a 2000
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=9977817