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Scalable real-time architectures and...

Krishnamurthy, Rajaram B.

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Scalable real-time architectures and hardware support for high-speed QoS packet schedulers.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Scalable real-time architectures and hardware support for high-speed QoS packet schedulers./
作者:	Krishnamurthy, Rajaram B.
面頁冊數:	168 p.
附註:	Source: Dissertation Abstracts International, Volume: 64-03, Section: B, page: 1336.
Contained By:	Dissertation Abstracts International64-03B.
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3084976

Scalable real-time architectures and hardware support for high-speed QoS packet schedulers.
Krishnamurthy, Rajaram B.

Scalable real-time architectures and hardware support for high-speed QoS packet schedulers. - 168 p.

Source: Dissertation Abstracts International, Volume: 64-03, Section: B, page: 1336.

Thesis (Ph.D.)--Georgia Institute of Technology, 2003.

Conventional wire-speed QoS packet scheduling architectures are inflexible and incur ASIC overhead costs. New hardware architectures are required to meet the QoS requirements of different streams at wire-speeds, without ASIC engineering overheads. An architectural framework is developed that helps guide development of architectures and physical realizations to meet the QoS needs of different streams, while balancing constraint-performance goals. A taxonomy of packet scheduling disciplines is developed that classifies into three different families—priority-class, fair-queueing and window-constrained. Software-based QoS packet schedulers can provide flexible scheduling support for application-level protocol data units. They are unable to exploit packet-level and stream-level parallelism efficiently for concurrent stream state maintenance. Also, bit-level parallelism in scheduler rules cannot be exploited efficiently for ordering streams. The ShareStreams (Scalable Hardware and Architectures for Stream Schedulers) hardware architecture exploits stream-level and packet-level parallelism. Stream service attributes are stored in Register Base blocks. Decision blocks are used to compare stream service attributes pairwise by exploiting bit-level parallelism in scheduler rules. Total priority ordering is provided by organizing Decision blocks in a recirculating shuffle-exchange network. ShareStreams is a scalable architecture and provides a number of architectural variants to trade execution time for lower hardware complexity in a predictable manner. A window-constrained scheduling discipline mapped to the ShareStreams architecture implemented in Xilinx Virtex II technology FPGAs can process 256 stream queues at 10 Gbps line-rates. A service-tag or priority-class scheduling discipline mapped to the ShareStreams architecture can process 4096 stream queues at 10 Gbps line-rates or 1024 stream queues at 40 Gbps line-rates with a Xilinx Virtex II FPGA. The ShareStreams system architecture uses a network or embedded processor, called a Stream processor for queueing and data movement, while decisions and stream selection are accelerated on a reconfigurable FPGA array. The system architecture can provide scheduling support for a mix of real-time and best-effort traffic streams. A host-based router implementation of the ShareStreams architecture can provide comparable performance with the MIT Click router, nearly 299,065 packets/second. The ShareStreams line-card configuration far exceeds the decision throughput provided by a number of vendor line-cards.Subjects--Topical Terms:

626642
Computer Science.

Scalable real-time architectures and hardware support for high-speed QoS packet schedulers.
LDR:03565nmm 2200289 4500 001 1859985
005 20041015084115.5
008 130614s2003 eng d
035 $a (UnM)AAI3084976
035 $a AAI3084976
040 $a UnM $c UnM
100 1 $a Krishnamurthy, Rajaram B. $3 1947638
245 1 0 $a Scalable real-time architectures and hardware support for high-speed QoS packet schedulers.
300 $a 168 p.
500 $a Source: Dissertation Abstracts International, Volume: 64-03, Section: B, page: 1336.
500 $a Directors: Karsten Schwan; Sudhakar Yalamanchili.
502 $a Thesis (Ph.D.)--Georgia Institute of Technology, 2003.
520 $a Conventional wire-speed QoS packet scheduling architectures are inflexible and incur ASIC overhead costs. New hardware architectures are required to meet the QoS requirements of different streams at wire-speeds, without ASIC engineering overheads. An architectural framework is developed that helps guide development of architectures and physical realizations to meet the QoS needs of different streams, while balancing constraint-performance goals. A taxonomy of packet scheduling disciplines is developed that classifies into three different families—priority-class, fair-queueing and window-constrained. Software-based QoS packet schedulers can provide flexible scheduling support for application-level protocol data units. They are unable to exploit packet-level and stream-level parallelism efficiently for concurrent stream state maintenance. Also, bit-level parallelism in scheduler rules cannot be exploited efficiently for ordering streams. The ShareStreams (Scalable Hardware and Architectures for Stream Schedulers) hardware architecture exploits stream-level and packet-level parallelism. Stream service attributes are stored in Register Base blocks. Decision blocks are used to compare stream service attributes pairwise by exploiting bit-level parallelism in scheduler rules. Total priority ordering is provided by organizing Decision blocks in a recirculating shuffle-exchange network. ShareStreams is a scalable architecture and provides a number of architectural variants to trade execution time for lower hardware complexity in a predictable manner. A window-constrained scheduling discipline mapped to the ShareStreams architecture implemented in Xilinx Virtex II technology FPGAs can process 256 stream queues at 10 Gbps line-rates. A service-tag or priority-class scheduling discipline mapped to the ShareStreams architecture can process 4096 stream queues at 10 Gbps line-rates or 1024 stream queues at 40 Gbps line-rates with a Xilinx Virtex II FPGA. The ShareStreams system architecture uses a network or embedded processor, called a Stream processor for queueing and data movement, while decisions and stream selection are accelerated on a reconfigurable FPGA array. The system architecture can provide scheduling support for a mix of real-time and best-effort traffic streams. A host-based router implementation of the ShareStreams architecture can provide comparable performance with the MIT Click router, nearly 299,065 packets/second. The ShareStreams line-card configuration far exceeds the decision throughput provided by a number of vendor line-cards.
590 $a School code: 0078.
650 4 $a Computer Science. $3 626642
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Engineering, System Science. $3 1018128
690 $a 0984
690 $a 0544
690 $a 0790
710 2 0 $a Georgia Institute of Technology. $3 696730
773 0 $t Dissertation Abstracts International $g 64-03B.
790 1 0 $a Schwan, Karsten, $e advisor
790 1 0 $a Yalamanchili, Sudhakar, $e advisor
790 $a 0078
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3084976