東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Software-based self-test and diagnos...

Chen, Li.

FindBook

Google Book

Amazon

博客來

Software-based self-test and diagnosis for processors and system-on-chips.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Software-based self-test and diagnosis for processors and system-on-chips./
作者:	Chen, Li.
面頁冊數:	165 p.
附註:	Source: Dissertation Abstracts International, Volume: 64-05, Section: B, page: 2311.
Contained By:	Dissertation Abstracts International64-05B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3090436
ISBN:	049638158X

Software-based self-test and diagnosis for processors and system-on-chips.
Chen, Li.

Software-based self-test and diagnosis for processors and system-on-chips. - 165 p.

Source: Dissertation Abstracts International, Volume: 64-05, Section: B, page: 2311.

Thesis (Ph.D.)--University of California, San Diego, 2003.

The rising cost of high-end testers and the need for systematic test generation methods capable of achieving high fault coverage drive the microprocessor industry's migration from functional test to structural test approaches such as scan testing. At the same time, the practice of at-speed functional test remains an irreplaceable part of microprocessor tests due to its unique benefits in testing speed defects, but cannot be continued in its present form due the associated high cost. To address this problem, we propose a new self-test paradigm, Software-Based Self-Test (SBST), for testing microprocessors and System-on-Chips (SoCs) containing embedded processors. To allow at-speed tests using low-cost testers, SBST enables processor self-test using a software tester embedded in the on-chip memory. The software tester consists of processor instructions and is generated using a divide-and-conquer approach that enables the systematic generation of instruction-level tests with high coverage on structural faults. We achieve this goal by (i) partitioning the processor-under-test into modules manageable by automatic test pattern generation (ATPG) algorithms, (ii) generating tests at the module level targeting at structural faults, and (iii) delivering tests to the module-under-test (MUT) using processor instructions. The use of instruction-imposed constraints bridges the gap between instruction-level test application and module-level test generation, while a novel simulation-based method is used to extract the constraints, requiring no architectural knowledge of the processor-under-test. We have automated the entire test generation process and successfully demonstrated it on two processors, including a commercial state-of-the-art embedded processor, the Xtensa(TM) processor from Tensilica Inc. In addition to detecting stuck-at faults within the processor, we extend the application of SBST in two directions. (i) We explore the fault diagnosis capability of SBST by systematically constructing a large number of diagnosis test programs capable of achieving a high diagnostic resolution on an overwhelming majority of faults in the processor. (ii) We extend SBST to test for crosstalk errors on system-level interconnects by utilizing the signal transitions occurring on the interconnects during the execution of instructions. The two extensions of SBST have been successfully demonstrated on a processor example and a processor-memory system.

ISBN: 049638158XSubjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Software-based self-test and diagnosis for processors and system-on-chips.
LDR:03350nmm 2200277 4500 001 1851123
005 20051216105415.5
008 130614s2003 eng d
020 $a 049638158X
035 $a (UnM)AAI3090436
035 $a AAI3090436
040 $a UnM $c UnM
100 1 $a Chen, Li. $3 1018741
245 1 0 $a Software-based self-test and diagnosis for processors and system-on-chips.
300 $a 165 p.
500 $a Source: Dissertation Abstracts International, Volume: 64-05, Section: B, page: 2311.
500 $a Chair: Sujit Dey.
502 $a Thesis (Ph.D.)--University of California, San Diego, 2003.
520 $a The rising cost of high-end testers and the need for systematic test generation methods capable of achieving high fault coverage drive the microprocessor industry's migration from functional test to structural test approaches such as scan testing. At the same time, the practice of at-speed functional test remains an irreplaceable part of microprocessor tests due to its unique benefits in testing speed defects, but cannot be continued in its present form due the associated high cost. To address this problem, we propose a new self-test paradigm, Software-Based Self-Test (SBST), for testing microprocessors and System-on-Chips (SoCs) containing embedded processors. To allow at-speed tests using low-cost testers, SBST enables processor self-test using a software tester embedded in the on-chip memory. The software tester consists of processor instructions and is generated using a divide-and-conquer approach that enables the systematic generation of instruction-level tests with high coverage on structural faults. We achieve this goal by (i) partitioning the processor-under-test into modules manageable by automatic test pattern generation (ATPG) algorithms, (ii) generating tests at the module level targeting at structural faults, and (iii) delivering tests to the module-under-test (MUT) using processor instructions. The use of instruction-imposed constraints bridges the gap between instruction-level test application and module-level test generation, while a novel simulation-based method is used to extract the constraints, requiring no architectural knowledge of the processor-under-test. We have automated the entire test generation process and successfully demonstrated it on two processors, including a commercial state-of-the-art embedded processor, the Xtensa(TM) processor from Tensilica Inc. In addition to detecting stuck-at faults within the processor, we extend the application of SBST in two directions. (i) We explore the fault diagnosis capability of SBST by systematically constructing a large number of diagnosis test programs capable of achieving a high diagnostic resolution on an overwhelming majority of faults in the processor. (ii) We extend SBST to test for crosstalk errors on system-level interconnects by utilizing the signal transitions occurring on the interconnects during the execution of instructions. The two extensions of SBST have been successfully demonstrated on a processor example and a processor-memory system.
590 $a School code: 0033.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Computer Science. $3 626642
690 $a 0544
690 $a 0984
710 2 0 $a University of California, San Diego. $3 1018093
773 0 $t Dissertation Abstracts International $g 64-05B.
790 1 0 $a Dey, Sujit, $e advisor
790 $a 0033
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3090436