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Power and clock distribution network...

Wang, Kai.

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Power and clock distribution networks optimization for deep sub-micron designs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Power and clock distribution networks optimization for deep sub-micron designs./
作者:	Wang, Kai.
面頁冊數:	127 p.
附註:	Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4752.
Contained By:	Dissertation Abstracts International65-09B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3145775
ISBN:	0496035746

Power and clock distribution networks optimization for deep sub-micron designs.
Wang, Kai.

Power and clock distribution networks optimization for deep sub-micron designs. - 127 p.

Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4752.

Thesis (Ph.D.)--University of California, Santa Barbara, 2004.

Computations in integrated circuits are carried out by the synchronized transportation of electro-charges from the primary inputs to the primary outputs of the circuits. Power and clock networks deliver global signals needed to do the computations. Delivering a time-varying current at a constant supply voltage with nominal variations is the purpose of the power distribution network. Whereas the clock signal defines a temporal reference for data movement, a clock distribution network delivers the clock signal from the clock source to the clock pins of registers. To provide high-quality clock signal, a designer must consider clock skew, power dissipation, and phase delay (latency) in the clock network design.

ISBN: 0496035746Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Power and clock distribution networks optimization for deep sub-micron designs.
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245 1 0 $a Power and clock distribution networks optimization for deep sub-micron designs.
300 $a 127 p.
500 $a Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4752.
500 $a Chair: Malgorzata Marek-Sadowska.
502 $a Thesis (Ph.D.)--University of California, Santa Barbara, 2004.
520 $a Computations in integrated circuits are carried out by the synchronized transportation of electro-charges from the primary inputs to the primary outputs of the circuits. Power and clock networks deliver global signals needed to do the computations. Delivering a time-varying current at a constant supply voltage with nominal variations is the purpose of the power distribution network. Whereas the clock signal defines a temporal reference for data movement, a clock distribution network delivers the clock signal from the clock source to the clock pins of registers. To provide high-quality clock signal, a designer must consider clock skew, power dissipation, and phase delay (latency) in the clock network design.
520 $a The integrity of power and clock signals significantly impacts the overall system performance and reliability. The performances of the power and clock distribution networks are also closely correlated, because power supply variations affect the clock timing while clock switching is one of the main sources of power supply noise. Technology scaling over the past few decades has enabled integrated circuits to speed up the computation rate with increasing clock frequencies, but the increase in the number of computing elements comes at the cost of higher power dissipation. The trend toward increasing power and clock frequency while reducing power supply voltage often causes the power supply and clock networks to experience larger amount of noise.
520 $a The timing characteristics of a clock signal also significantly affect the potential performance of combinational circuits. The potential performance indicates how much improvement could be made through future optimization and can be effectively measured by the so-called potential slack, which is the maximal amount of slack that can be potentially used for optimization. Furthermore, potential slack of a logic block is affected by the signal arrival and required times at the primary inputs and outputs, which in turn are decided by the arrival times of the clock signals at the launching flip-flops. The clock arrival times can be adjusted through clock skew scheduling. For a system consisting of a set of combinational logic blocks and a clock distribution network feeding clock signals to each block, a synergistic blend of potential slack calculation and clock skew scheduling could improve the total potential slack of all logic blocks in the system.
520 $a In this dissertation, we focus on the problems of optimizing power and clock distribution networks for deep sub-micron designs. This dissertation consists of three parts. In the first part, we propose a new power supply network optimization methodology based on the multi-grid technique. In the second part, we propose a novel clock network sizing technique subject to general skew constraints. Our technique is based on sequential linear programming and time-domain analysis to provide accurate delay and skew results, and takes into account the impact of power supply variations. We also demonstrate its application to peak current reduction. In the third part, we first present a linear-programming based approach for potential slack calculation, and then we combine our technique with clock network optimization to further improve the total potential slack of all the combinational logic blocks.
590 $a School code: 0035.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 0 $a University of California, Santa Barbara. $3 1017586
773 0 $t Dissertation Abstracts International $g 65-09B.
790 1 0 $a Marek-Sadowska, Malgorzata, $e advisor
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791 $a Ph.D.
792 $a 2004
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3145775