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Implementation of real-time feature ...

Sahoo, Subrat.

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Implementation of real-time feature detection and object tracking on a low-cost reconfigurable computing system.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Implementation of real-time feature detection and object tracking on a low-cost reconfigurable computing system./
作者:	Sahoo, Subrat.
面頁冊數:	81 p.
附註:	Source: Masters Abstracts International, Volume: 42-06, page: 2332.
Contained By:	Masters Abstracts International42-06.
標題:	Engineering, System Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=MQ90694
ISBN:	0612906949

Implementation of real-time feature detection and object tracking on a low-cost reconfigurable computing system.
Sahoo, Subrat.

Implementation of real-time feature detection and object tracking on a low-cost reconfigurable computing system. - 81 p.

Source: Masters Abstracts International, Volume: 42-06, page: 2332.

Thesis (M.Sc.)--University of Guelph (Canada), 2004.

In this thesis, we present a real-time feature detection and object tracking system that is implemented on a low cost FPGA architecture. The algorithms are simulated in various environments to verify the real-time performance. A high-level programming language, Handel-C, is used to design and simulate in a DK1 design environment, and the design is synthesized by Xilinx WebPack synthesis tool. The final design is implemented on a low cost Xilinx Spartan-II-based FPGA device.

ISBN: 0612906949Subjects--Topical Terms:

1018128
Engineering, System Science.

Implementation of real-time feature detection and object tracking on a low-cost reconfigurable computing system.
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500 $a Advisers: Otman A. Basir; Gauri S. Mittal.
502 $a Thesis (M.Sc.)--University of Guelph (Canada), 2004.
520 $a In this thesis, we present a real-time feature detection and object tracking system that is implemented on a low cost FPGA architecture. The algorithms are simulated in various environments to verify the real-time performance. A high-level programming language, Handel-C, is used to design and simulate in a DK1 design environment, and the design is synthesized by Xilinx WebPack synthesis tool. The final design is implemented on a low cost Xilinx Spartan-II-based FPGA device.
520 $a The thesis also tries to implement the various algorithms in modular ways and tests these configurations on the FPGA device separately. The final design is implemented by merging all modular code in real-time.
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