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Multilevel VLSI placement in very de...

Hu, Bo.

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Multilevel VLSI placement in very deep sub-micron technology.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Multilevel VLSI placement in very deep sub-micron technology./
Author:	Hu, Bo.
Description:	158 p.
Notes:	Source: Dissertation Abstracts International, Volume: 65-06, Section: B, page: 3066.
Contained By:	Dissertation Abstracts International65-06B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3136890
ISBN:	049684086X

Multilevel VLSI placement in very deep sub-micron technology.
Hu, Bo.

Multilevel VLSI placement in very deep sub-micron technology. - 158 p.

Source: Dissertation Abstracts International, Volume: 65-06, Section: B, page: 3066.

Thesis (Ph.D.)--University of California, Santa Barbara, 2004.

As 90nm process technology starts to merge into the mainstream manufacture of high-end ICs, the demand for better-quality Electrical Design Automation (EDA) tools, especially physical design tools, grows rapidly. Among the IC physical design tools, the placer is one of the most critical tools in determining the overall quality of the whole tool suite. The placer in sub-90nm technology is not only required to be efficient to address a full spectrum of deep sub-micron effects, interconnect dominance, IR drop, signal integrity etc., it should also produce the stable and predictable result to assist in design convergence.

ISBN: 049684086XSubjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Multilevel VLSI placement in very deep sub-micron technology.
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100 1 $a Hu, Bo. $3 1264684
245 1 0 $a Multilevel VLSI placement in very deep sub-micron technology.
300 $a 158 p.
500 $a Source: Dissertation Abstracts International, Volume: 65-06, Section: B, page: 3066.
500 $a Chair: Malgorzata Marek-Sadowska.
502 $a Thesis (Ph.D.)--University of California, Santa Barbara, 2004.
520 $a As 90nm process technology starts to merge into the mainstream manufacture of high-end ICs, the demand for better-quality Electrical Design Automation (EDA) tools, especially physical design tools, grows rapidly. Among the IC physical design tools, the placer is one of the most critical tools in determining the overall quality of the whole tool suite. The placer in sub-90nm technology is not only required to be efficient to address a full spectrum of deep sub-micron effects, interconnect dominance, IR drop, signal integrity etc., it should also produce the stable and predictable result to assist in design convergence.
520 $a In this dissertation, we address efficiency, predictability and stability in developing a multi-level placement flow for the emerging sub-90nm technologies. First, we will present a fine-granularity clustering technique to accelerate the placement while maintaining the consistent placement quality. Second, we will introduce pseudo connections in conventional non-constrained quadratic-programming formulation to solve the inherent problem of cell overlapping in global placement. In addition, we will propose a multi-objective-driven incremental placement approach to simultaneously optimize a circuit's routability, performance, and power consumption. Based upon these techniques, we build a multi-level placement flow. Experimental data confirms that the new flow is not only efficient and stable, but also capable of producing predictable interconnects.
590 $a School code: 0035.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Computer Science. $3 626642
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710 2 0 $a University of California, Santa Barbara. $3 1017586
773 0 $t Dissertation Abstracts International $g 65-06B.
790 1 0 $a Marek-Sadowska, Malgorzata, $e advisor
790 $a 0035
791 $a Ph.D.
792 $a 2004
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3136890