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Effects of dimensional nanoscaling o...
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Sharma, Ashwani Kumar.
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Effects of dimensional nanoscaling on the optical and electronic properties of silicon films-walls-wires.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Effects of dimensional nanoscaling on the optical and electronic properties of silicon films-walls-wires./
作者:
Sharma, Ashwani Kumar.
面頁冊數:
295 p.
附註:
Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4749.
Contained By:
Dissertation Abstracts International65-09B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3148065
ISBN:
0496071572
Effects of dimensional nanoscaling on the optical and electronic properties of silicon films-walls-wires.
Sharma, Ashwani Kumar.
Effects of dimensional nanoscaling on the optical and electronic properties of silicon films-walls-wires.
- 295 p.
Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4749.
Thesis (Ph.D.)--The University of New Mexico, 2004.
A detailed experimental and theoretical investigation focused upon evaluating the effects of dimensional nanoscaling of silicon features on the optical and electronic properties of the material is presented. The feature dimensions in this work ranged from ∼200nm down to ∼10nm. This range represents the transition region from material bulk properties towards the onset of quantization. These structures were fabricated on silicon-on-insulator using interferometric lithography, reactive-ion-etching and thermal oxidation methods. In order to investigate the optical and electronic properties, the nanostructures were configured in a two terminal metal-semiconductor-metal test device arrangement. The metal-semiconductor interfaces formed Schottky barrier type contacts. The metal-semiconductor-metal configuration was chosen for this study due to its practicality in photonic and electronic parameter characterization and the ease of device fabrication. Characterization methods included optical steady-state DC measurements, dark current measurements, spectral response measurements as a function of wavelength, and transient time response measurements using a modified version of the Haynes-Shockley experiment for evaluating the carrier mobility as a function of feature size. Results show that the total carrier drift-diffusion dependent conduction for same biasing conditions increased as the feature dimension was reduced from ∼200nm to ∼10nm. The transient time response measurements show that the low field electron mobility can be increased in the best case at room temperature from ∼1000 cm2/V-s to ∼4000 cm2/V-s as the cross-sectional area becomes narrower due to confinement effects. Theoretical models for optical coupling and electronic transport properties are provided to give physical insight at these small scales. To demonstrate the potentials of nanoscaling that would benefit the Si CMOS industry, a high mobility ∼50nm nanowire wrap-around-gate MOSFET was developed as a proof of concept device that showed 3X improvement in the current driving capability over comparable conventional planar slab gate length devices due reduced transverse scattering effects.
ISBN: 0496071572Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
Effects of dimensional nanoscaling on the optical and electronic properties of silicon films-walls-wires.
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A detailed experimental and theoretical investigation focused upon evaluating the effects of dimensional nanoscaling of silicon features on the optical and electronic properties of the material is presented. The feature dimensions in this work ranged from ∼200nm down to ∼10nm. This range represents the transition region from material bulk properties towards the onset of quantization. These structures were fabricated on silicon-on-insulator using interferometric lithography, reactive-ion-etching and thermal oxidation methods. In order to investigate the optical and electronic properties, the nanostructures were configured in a two terminal metal-semiconductor-metal test device arrangement. The metal-semiconductor interfaces formed Schottky barrier type contacts. The metal-semiconductor-metal configuration was chosen for this study due to its practicality in photonic and electronic parameter characterization and the ease of device fabrication. Characterization methods included optical steady-state DC measurements, dark current measurements, spectral response measurements as a function of wavelength, and transient time response measurements using a modified version of the Haynes-Shockley experiment for evaluating the carrier mobility as a function of feature size. Results show that the total carrier drift-diffusion dependent conduction for same biasing conditions increased as the feature dimension was reduced from ∼200nm to ∼10nm. The transient time response measurements show that the low field electron mobility can be increased in the best case at room temperature from ∼1000 cm2/V-s to ∼4000 cm2/V-s as the cross-sectional area becomes narrower due to confinement effects. Theoretical models for optical coupling and electronic transport properties are provided to give physical insight at these small scales. To demonstrate the potentials of nanoscaling that would benefit the Si CMOS industry, a high mobility ∼50nm nanowire wrap-around-gate MOSFET was developed as a proof of concept device that showed 3X improvement in the current driving capability over comparable conventional planar slab gate length devices due reduced transverse scattering effects.
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http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3148065
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