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Architectural and compiler technique...

Wu, Qiang.

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Architectural and compiler techniques for microprocessor power and performance management.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Architectural and compiler techniques for microprocessor power and performance management./
Author:	Wu, Qiang.
Description:	123 p.
Notes:	Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2092.
Contained By:	Dissertation Abstracts International67-04B.
Subject:	Computer Science. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3214597
ISBN:	9780542650567

Architectural and compiler techniques for microprocessor power and performance management.
Wu, Qiang.

Architectural and compiler techniques for microprocessor power and performance management. - 123 p.

Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2092.

Thesis (Ph.D.)--Princeton University, 2006.

As computing technology continues to progress very rapidly, many technical challenges emerge. One of these is the issue of power dissipation. Indeed, power delivery and dissipation are becoming primary limiters of performance and integration for microprocessors. In response, architectural and software level power-reduction techniques, which extend traditional circuit-level energy techniques, have gained more and more attention and become an active research area in the last few years.

ISBN: 9780542650567Subjects--Topical Terms:

626642
Computer Science.

Architectural and compiler techniques for microprocessor power and performance management.
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020 $a 9780542650567
035 $a (UMI)AAI3214597
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100 1 $a Wu, Qiang. $3 1917772
245 1 0 $a Architectural and compiler techniques for microprocessor power and performance management.
300 $a 123 p.
500 $a Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2092.
500 $a Adviser: Doug Clark.
502 $a Thesis (Ph.D.)--Princeton University, 2006.
520 $a As computing technology continues to progress very rapidly, many technical challenges emerge. One of these is the issue of power dissipation. Indeed, power delivery and dissipation are becoming primary limiters of performance and integration for microprocessors. In response, architectural and software level power-reduction techniques, which extend traditional circuit-level energy techniques, have gained more and more attention and become an active research area in the last few years.
520 $a The work in this thesis focuses on one important problem in this area, namely dynamic power and performance management in high-performance processors. Dynamic adaptive techniques are appealing because they offer the ability to adjust on the fly according to the current run-time power and performance situation. This thesis investigates architectural and compiler techniques for controlling power and performance in microprocessors. The overall contributions of this work are the proposed new concepts, methods, and framework for intelligent power and performance management.
520 $a Specifically, this work has had two major thrusts. First, formal control-theoretic techniques will be discussed in the context of hardware-based energy control. The environment is a multiple clock domain processor. An analytical system model is first proposed that describes relationships among performance demand, capability, and clock frequency. A controller is then designed to balance the speeds of different clock islands. Experimental results show that the proposed technique is 2--3 times more efficient in terms of energy delay product improvement, compared to a previous heuristic approach. In addition, the new technique is more robust with a guaranteed stability margin even under extreme cases. For the above design, both fixed-interval and adaptive interval control schemes have been investigated. Second, software-layer energy control opportunities are explored in a general dynamic compilation system. It is shown that a dynamic compiler driven scheme has several unique features and advantages over existing energy control schemes. Such a scheme is then designed, implemented, and deployed on real hardware (with a Pentium-M processor). Experimental results from physical power measurements show up to 70% energy saving is accomplished for SPEC benchmarks. In addition, because of its orthogonal features and advantages, the dynamic compiler driven scheme can be an effective complement to existing hardware-based energy control schemes.
590 $a School code: 0181.
650 4 $a Computer Science. $3 626642
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710 2 0 $a Princeton University. $3 645579
773 0 $t Dissertation Abstracts International $g 67-04B.
790 1 0 $a Clark, Doug, $e advisor
790 $a 0181
791 $a Ph.D.
792 $a 2006
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3214597