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Designing energy-efficient and relia...

Li, Lin.

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Designing energy-efficient and reliable caches and interconnects.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Designing energy-efficient and reliable caches and interconnects./
Author:	Li, Lin.
Description:	155 p.
Notes:	Source: Dissertation Abstracts International, Volume: 66-10, Section: B, page: 5501.
Contained By:	Dissertation Abstracts International66-10B.
Subject:	Computer Science. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3193207
ISBN:	9780542359576

Designing energy-efficient and reliable caches and interconnects.
Li, Lin.

Designing energy-efficient and reliable caches and interconnects. - 155 p.

Source: Dissertation Abstracts International, Volume: 66-10, Section: B, page: 5501.

Thesis (Ph.D.)--The Pennsylvania State University, 2005.

The minimum feature size of VLSI technology has shrunk exponentially in the past three decades and is expected to continue this trend in the near future. This phenomenon has resulted in an increase in the number of transistors integrated onto a single chip, a decrease in supply voltages and threshold voltages, and an increase in clock frequencies for each generation. The scaling of these design parameters impacts digital circuits and systems design in two important ways: a dramatic increase in energy consumption and a deterioration of reliability.

ISBN: 9780542359576Subjects--Topical Terms:

626642
Computer Science.

Designing energy-efficient and reliable caches and interconnects.
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245 1 0 $a Designing energy-efficient and reliable caches and interconnects.
300 $a 155 p.
500 $a Source: Dissertation Abstracts International, Volume: 66-10, Section: B, page: 5501.
500 $a Advisers: Mary Jane Irwin; Vijaykrishnan Narayanan.
502 $a Thesis (Ph.D.)--The Pennsylvania State University, 2005.
520 $a The minimum feature size of VLSI technology has shrunk exponentially in the past three decades and is expected to continue this trend in the near future. This phenomenon has resulted in an increase in the number of transistors integrated onto a single chip, a decrease in supply voltages and threshold voltages, and an increase in clock frequencies for each generation. The scaling of these design parameters impacts digital circuits and systems design in two important ways: a dramatic increase in energy consumption and a deterioration of reliability.
520 $a This thesis proposes design methodologies and techniques at the micro-architecture level for improving energy-efficiency and reliability in cache memories and on-chip inter-connects.
520 $a First, architectural techniques are proposed to reduce both leakage and dynamic energy consumption in cache memories. State-preserving and state-destroying leakage control mechanisms are integrated into L2 cache to reduce leakage energy consumption due to the data duplication across different levels of cache hierarchy. A crossbar-connected cache configuration is proposed for on-chip multiprocessor systems. The dynamic energy consumption in L1 cache is reduced due to sharing a single, banked cache among processors.
520 $a Next, the impact of crosstalk noise on the reliability of on-chip interconnects is investigated, and a crosstalk-aware interconnect is proposed. A crosstalk analyzer circuit is designed to be incorporated into the sender side of the bus to estimate the delay based on the data pattern to be transmitted. Then, a variable cycle transmission mechanism is implemented to use a faster clock and dynamically control the number of cycles required for transmission.
520 $a Finally, the interaction between energy consumption and reliability is studied. Based on the soft error injection implemented in the cache system of SimpleScalar simulator, the impact of two architectural-level leakage reduction approaches, drowsy cache and cache decay, on the data reliability are evaluated. Then, providing data reliability in an energy-efficient fashion is investigated. An adaptive error coding scheme is proposed that treats dirty and clean data cache blocks differently. Furthermore, an early-write-back scheme is introduced to enhance the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Adaptive error protection scheme is also applied to on-chip interconnects for energy efficiency, where the type of error detection coding scheme is modulated dynamically based on the dynamic variations observed in noise behavior.
590 $a School code: 0176.
650 4 $a Computer Science. $3 626642
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0984
690 $a 0544
710 2 0 $a The Pennsylvania State University. $3 699896
773 0 $t Dissertation Abstracts International $g 66-10B.
790 1 0 $a Irwin, Mary Jane, $e advisor
790 1 0 $a Narayanan, Vijaykrishnan, $e advisor
790 $a 0176
791 $a Ph.D.
792 $a 2005
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3193207