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Modeling, circuits and architectures...

Li, Fei.

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Modeling, circuits and architectures for power-efficient FPGAs.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Modeling, circuits and architectures for power-efficient FPGAs./
作者:	Li, Fei.
面頁冊數:	105 p.
附註:	Source: Dissertation Abstracts International, Volume: 67-01, Section: B, page: 0440.
Contained By:	Dissertation Abstracts International67-01B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3202789
ISBN:	9780542508905

Modeling, circuits and architectures for power-efficient FPGAs.
Li, Fei.

Modeling, circuits and architectures for power-efficient FPGAs. - 105 p.

Source: Dissertation Abstracts International, Volume: 67-01, Section: B, page: 0440.

Thesis (Ph.D.)--University of California, Los Angeles, 2005.

As VLSI advances to the realm of ultra-deep sub-micron (USDM) technologies and giga-scale designs, application specific integrated circuit (ASIC) becomes extremely costly and time-consuming to design and fabricate. Field programmable gate array (FPGA) provides an attractive computing platform due to its low NRE (non-recurring engineering) cost and short time-to-market. However, existing FPGA circuits and architectures are highly power inefficient and power consumption is likely the largest limitation for FPGAs in nanometer technology. This dissertation studies the power modeling of FPGAs and designs power efficient FPGA circuits and architectures. Concerning FPGA power modeling, we develop a mixed-level power model for parameterized FPGA architectures. It considers both dynamic and leakage power, and combines switch-level models for interconnects and macromodels for logic cells. Experiments show that our power model achieves a high fidelity compared to the time-consuming SPICE simulation and the average error is around 8%. We further study the power characteristics of existing FPGA architectures in 100nm technology, and show that interconnect power is dominant and leakage power becomes significant. We also show that logic block architecture tuning can reduce total FPGA energy by 48% with merely 12% delay increase. In addition, FPGA energy and area are reduced at the same time by tuning lookup table (LUT) and logic cluster sizes.

ISBN: 9780542508905Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Modeling, circuits and architectures for power-efficient FPGAs.
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502 $a Thesis (Ph.D.)--University of California, Los Angeles, 2005.
520 $a As VLSI advances to the realm of ultra-deep sub-micron (USDM) technologies and giga-scale designs, application specific integrated circuit (ASIC) becomes extremely costly and time-consuming to design and fabricate. Field programmable gate array (FPGA) provides an attractive computing platform due to its low NRE (non-recurring engineering) cost and short time-to-market. However, existing FPGA circuits and architectures are highly power inefficient and power consumption is likely the largest limitation for FPGAs in nanometer technology. This dissertation studies the power modeling of FPGAs and designs power efficient FPGA circuits and architectures. Concerning FPGA power modeling, we develop a mixed-level power model for parameterized FPGA architectures. It considers both dynamic and leakage power, and combines switch-level models for interconnects and macromodels for logic cells. Experiments show that our power model achieves a high fidelity compared to the time-consuming SPICE simulation and the average error is around 8%. We further study the power characteristics of existing FPGA architectures in 100nm technology, and show that interconnect power is dominant and leakage power becomes significant. We also show that logic block architecture tuning can reduce total FPGA energy by 48% with merely 12% delay increase. In addition, FPGA energy and area are reduced at the same time by tuning lookup table (LUT) and logic cluster sizes.
520 $a Concerning FPGA logic power reduction, we propose field programmable supply voltage and applies it to FPGA logic blocks. To reduce leakage under different Vdd levels, we first propose a constant-leakage Vdd scaling at manufacture time for FPGA circuits with bounded performance change, and further apply high threshold voltage to all configuration SRAM cells without introducing runtime performance loss. We then design FPGA logic fabrics using dual Vdd levels, and show that field programmable supply voltage is required to obtain a satisfactory performance and power trade-off. With a simple yet practical CAD flow to leverage field programmable dual-Vdd logic fabrics, we carry out a highly quantitative study using placed and routed benchmark applications and area, delay and power models obtained from detailed circuit designs in 100nm technology. (Abstract shortened by UMI.)
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