東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Deep submicron CMOS VLSI circuit rel...

Li, Xiaojun.

FindBook

Google Book

Amazon

博客來

Deep submicron CMOS VLSI circuit reliability modeling, simulation and design.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Deep submicron CMOS VLSI circuit reliability modeling, simulation and design./
作者:	Li, Xiaojun.
面頁冊數:	211 p.
附註:	Source: Dissertation Abstracts International, Volume: 66-12, Section: B, page: 6820.
Contained By:	Dissertation Abstracts International66-12B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3201972
ISBN:	9780542471162

Deep submicron CMOS VLSI circuit reliability modeling, simulation and design.
Li, Xiaojun.

Deep submicron CMOS VLSI circuit reliability modeling, simulation and design. - 211 p.

Source: Dissertation Abstracts International, Volume: 66-12, Section: B, page: 6820.

Thesis (Ph.D.)--University of Maryland, College Park, 2005.

CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication.

ISBN: 9780542471162Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Deep submicron CMOS VLSI circuit reliability modeling, simulation and design.
LDR:03194nmm 2200289 4500 001 1823076
005 20061130093114.5
008 130610s2005 eng d
020 $a 9780542471162
035 $a (UnM)AAI3201972
035 $a AAI3201972
040 $a UnM $c UnM
100 1 $a Li, Xiaojun. $3 1286746
245 1 0 $a Deep submicron CMOS VLSI circuit reliability modeling, simulation and design.
300 $a 211 p.
500 $a Source: Dissertation Abstracts International, Volume: 66-12, Section: B, page: 6820.
500 $a Chair: Joseph B. Bernstein.
502 $a Thesis (Ph.D.)--University of Maryland, College Park, 2005.
520 $a CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication.
520 $a This work develops a new SPICE reliability simulation method that shifts the focus of reliability analysis from device wearout to circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models are proposed for the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias Temperature Instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current waveforms. Then corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, SPICE simulation is performed again to check circuit functionality and analyze the impact of device wearout on circuit operation. Device wearout effects are lumped into a very limited number of failure equivalent circuit model parameters, and circuit performance degradation and functionality are determined by the magnitude of these parameters.
520 $a In this new method, it is unnecessary to perform a large number of small-step SPICE simulation iterations. Therefore, simulation time is obviously shortened in comparison to other tools. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE model parameters, need to be accurately characterized at each interim wearout process. Thus device testing and parameter extraction work are also significantly simplified. These advantages will allow circuit designers to perform quick and efficient circuit reliability analyses and to develop practical guidelines for reliable electronic designs.
590 $a School code: 0117.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a University of Maryland, College Park. $3 657686
773 0 $t Dissertation Abstracts International $g 66-12B.
790 1 0 $a Bernstein, Joseph B., $e advisor
790 $a 0117
791 $a Ph.D.
792 $a 2005
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3201972