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VLSI design optimization for lifting...

Li, Jian.

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VLSI design optimization for lifting scheme DWT.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	VLSI design optimization for lifting scheme DWT./
作者:	Li, Jian.
面頁冊數:	70 p.
附註:	Source: Masters Abstracts International, Volume: 44-02, page: 0996.
Contained By:	Masters Abstracts International44-02.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1428951
ISBN:	9780542330575

VLSI design optimization for lifting scheme DWT.
Li, Jian.

VLSI design optimization for lifting scheme DWT. - 70 p.

Source: Masters Abstracts International, Volume: 44-02, page: 0996.

Thesis (M.S.)--Michigan State University, 2005.

Neuroprosthetics can benefit greatly from area and power efficient signal processing circuitry suitable for implanting alongside miniature neural probes that interface to the nervous system. This thesis identifies an optimal VLSI architecture for computing a 1-dimensional multilevel discrete wavelet transform for multiple electrode channels simultaneously. The architecture is based on the lifting-scheme for wavelet computation and integer fixed-point precision for real-time processing under constraints imposed by implantability requirements. Two different computational node designs have been explored and compared to identify an optimal approach that minimizes power and chip area for a given number of levels and channels. Low power and low size computation elements: multiplier and adder ware realized. Results demonstrate that on-chip computation is feasible prior to data transmission.

ISBN: 9780542330575Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

VLSI design optimization for lifting scheme DWT.
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502 $a Thesis (M.S.)--Michigan State University, 2005.
520 $a Neuroprosthetics can benefit greatly from area and power efficient signal processing circuitry suitable for implanting alongside miniature neural probes that interface to the nervous system. This thesis identifies an optimal VLSI architecture for computing a 1-dimensional multilevel discrete wavelet transform for multiple electrode channels simultaneously. The architecture is based on the lifting-scheme for wavelet computation and integer fixed-point precision for real-time processing under constraints imposed by implantability requirements. Two different computational node designs have been explored and compared to identify an optimal approach that minimizes power and chip area for a given number of levels and channels. Low power and low size computation elements: multiplier and adder ware realized. Results demonstrate that on-chip computation is feasible prior to data transmission.
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