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Analysis and design of high-speed hi...

Wang, Jing.

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Analysis and design of high-speed high-resolution analog-to-digital converter.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Analysis and design of high-speed high-resolution analog-to-digital converter./
作者:	Wang, Jing.
面頁冊數:	105 p.
附註:	Source: Dissertation Abstracts International, Volume: 64-04, Section: B, page: 1853.
Contained By:	Dissertation Abstracts International64-04B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3088192
ISBN:	9780496359547

Analysis and design of high-speed high-resolution analog-to-digital converter.
Wang, Jing.

Analysis and design of high-speed high-resolution analog-to-digital converter. - 105 p.

Source: Dissertation Abstracts International, Volume: 64-04, Section: B, page: 1853.

Thesis (Ph.D.)--Texas A&M University, 2003.

A pipeline ADC (Analog-to-Digital Converter) architecture is proposed. The ADC is composed of a unique first stage and a conventional second stage. A track-hold and an operational amplifier have been proposed to be used in the ADC system.

ISBN: 9780496359547Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Analysis and design of high-speed high-resolution analog-to-digital converter.
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245 1 0 $a Analysis and design of high-speed high-resolution analog-to-digital converter.
300 $a 105 p.
500 $a Source: Dissertation Abstracts International, Volume: 64-04, Section: B, page: 1853.
500 $a Chair: Franco Maloberti.
502 $a Thesis (Ph.D.)--Texas A&M University, 2003.
520 $a A pipeline ADC (Analog-to-Digital Converter) architecture is proposed. The ADC is composed of a unique first stage and a conventional second stage. A track-hold and an operational amplifier have been proposed to be used in the ADC system.
520 $a The first stage is implemented in the transistor level. It can generate an analog residue at 10-bit accuracy level with 100MHz sampling frequency. The track-hold has a 14-bit linearity with 13MHz input frequency and 100MHz sampling frequency. The power supply is +/-1.65V for the overall system. The circuits are designed using a 0.18 mum digital CMOS process and the layout is finished.
520 $a Two chips have been fabricated and tested. The track-hold chip consumes 23.76mW power from a +/-1.65 V power supply. The track-hold has 11-bit resolution. The ADC chip is functional with the proposed track-hold.
520 $a The results proved the research ideas.
590 $a School code: 0803.
650 4 $a Engineering, Electronics and Electrical. $3 626636
650 4 $a Computer Science. $3 626642
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690 $a 0984
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790 1 0 $a Maloberti, Franco, $e advisor
790 $a 0803
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3088192