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Design verification for sequential s...

Zhang, Liang.

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Design verification for sequential systems at various abstraction levels.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design verification for sequential systems at various abstraction levels./
作者:	Zhang, Liang.
面頁冊數:	139 p.
附註:	Source: Dissertation Abstracts International, Volume: 65-12, Section: B, page: 6577.
Contained By:	Dissertation Abstracts International65-12B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3157759
ISBN:	049690079X

Design verification for sequential systems at various abstraction levels.
Zhang, Liang.

Design verification for sequential systems at various abstraction levels. - 139 p.

Source: Dissertation Abstracts International, Volume: 65-12, Section: B, page: 6577.

Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 2005.

With the ever increasing complexity of digital systems, functional verification has become a daunting task to circuit designers. Functional verification alone often surpasses 70% of the total development cost and the situation has been projected to continue to worsen. The most critical limitations of existing techniques are the capacity issue and the run-time issue.

ISBN: 049690079XSubjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Design verification for sequential systems at various abstraction levels.
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245 1 0 $a Design verification for sequential systems at various abstraction levels.
300 $a 139 p.
500 $a Source: Dissertation Abstracts International, Volume: 65-12, Section: B, page: 6577.
500 $a Chair: Michael S. Hsiao.
502 $a Thesis (Ph.D.)--Virginia Polytechnic Institute and State University, 2005.
520 $a With the ever increasing complexity of digital systems, functional verification has become a daunting task to circuit designers. Functional verification alone often surpasses 70% of the total development cost and the situation has been projected to continue to worsen. The most critical limitations of existing techniques are the capacity issue and the run-time issue.
520 $a This dissertation addresses the functional verification problem using a unified approach, which utilizes different core algorithms at various abstraction levels.
520 $a At the logic level, we focus on incorporating a set of novel ideas to existing formal verification approaches. First, we present a number of powerful optimizations to improve the performance and capacity of a typical SAT-based bounded model checking framework. Secondly, we present a novel method for performing dynamic abstraction within a framework for abstraction-refinement based model checking. Experiments on a wide range of industrial designs have shown that the proposed optimizations consistently provide between 1--2 orders of magnitude speedup and can be extremely useful in enhancing the efficacy of existing formal verification algorithms.
520 $a At the register transfer level, where the formal verification is less likely to succeed, we developed an efficient ATPG-based validation framework, which leverages the high level circuit information and an improved observability-enhanced coverage to generate high quality validation sequences. Experiments show that our approach is able to generate high quality validation vectors, which achieve both high tag coverage and high bug coverage with extremely low computational cost.
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