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Evolutionary and Disruptive Approach...

Dadgour, Hamed F.

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Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics./
作者:	Dadgour, Hamed F.
面頁冊數:	269 p.
附註:	Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: 0423.
Contained By:	Dissertation Abstracts International72-01B.
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3427837
ISBN:	9781124330273

Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics.
Dadgour, Hamed F.

Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics. - 269 p.

Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: 0423.

Thesis (Ph.D.)--University of California, Santa Barbara, 2010.

With growing concerns over the energy crisis, the semiconductor industry is motivated to reduce its energy consumption by deploying emerging nanotechnologies. This research contributes to such attempts by (1) introducing novel methods to evaluate energy consumption of nanoscale circuits and systems, (2) improving the energy efficiency of micro-architectures by employing innovative circuit design methods and (3) investigating the implications of employing Nano-Electro-Mechanical Switches (NEMS) to reduce the power consumption of VLSI circuits.

ISBN: 9781124330273Subjects--Topical Terms:

1669061
Engineering, Computer.

Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics.
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245 1 0 $a Evolutionary and Disruptive Approaches for Designing Next-Generation Ultra Energy-Efficient Electronics.
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500 $a Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: 0423.
500 $a Adviser: Kaustav Banerjee.
502 $a Thesis (Ph.D.)--University of California, Santa Barbara, 2010.
520 $a With growing concerns over the energy crisis, the semiconductor industry is motivated to reduce its energy consumption by deploying emerging nanotechnologies. This research contributes to such attempts by (1) introducing novel methods to evaluate energy consumption of nanoscale circuits and systems, (2) improving the energy efficiency of micro-architectures by employing innovative circuit design methods and (3) investigating the implications of employing Nano-Electro-Mechanical Switches (NEMS) to reduce the power consumption of VLSI circuits.
520 $a In the first part of the dissertation, we propose an accurate method for full-chip estimation of energy consumption in VLSI circuits considering the impact of parameter fluctuations. Furthermore, a novel variation-tolerant wide fan-in dynamic OR gate (a key component used in memory designs) will be introduced, which enables circuit designers to simultaneously improve the energy-efficiency as well as reliability. I will also introduce a new source of threshold voltage variation, which results in higher energy consumption in nano-scaled designs. The new source of process variation is unique to high-k/metal gate transistors and is caused by the dependency of work function of metal grains on their orientations. The implications of this source of random variations on the energy consumption, reliability and performance of SRAM cells will be investigate.
520 $a In the second part of the dissertation, the implications of employing NEMS devices for improving the energy efficiency of circuits and systems will be discussed. NEMS transistors, while disruptive, are attractive devices because they offer unbeatable subthreshold characteristics (energy efficiency) compared to all other emerging solid-state transistors. In this dissertation, the implications of employing various NEMS devices on digital circuit design are explored. Particularly, a new class of NEMS devices called Laterally-Actuated Double-Gate NEMS transistor is introduced and analyzed. It is shown that such devices can be employed to implement highly energy-efficient and ultra compact XOR gates, which are the key building blocks for more complex computational units. The lateral NEMS device also creates new opportunities in Boolean logic minimization and seems promising for implementing high-performance arithmetic modules (such as Adders). A comprehensive scaling analysis of the NEMS devices is also conducted to identify the key challenges that must be overcome before such transistors can be incorporated in the mainstream IC technologies.
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790 1 0 $a Banerjee, Kaustav, $e advisor
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790 1 0 $a Wang, Li C. $e committee member
790 1 0 $a Long, Steve $e committee member
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