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Real-time simulation of dynamic vehi...

Monga, Madhu.

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Real-time simulation of dynamic vehicle models using high performance reconfigurable computing platforms.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Real-time simulation of dynamic vehicle models using high performance reconfigurable computing platforms./
作者:	Monga, Madhu.
面頁冊數:	79 p.
附註:	Source: Masters Abstracts International, Volume: 49-03, page: 1941.
Contained By:	Masters Abstracts International49-03.
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1488058
ISBN:	9781124431420

Real-time simulation of dynamic vehicle models using high performance reconfigurable computing platforms.
Monga, Madhu.

Real-time simulation of dynamic vehicle models using high performance reconfigurable computing platforms. - 79 p.

Source: Masters Abstracts International, Volume: 49-03, page: 1941.

Thesis (M.S.)--Iowa State University, 2010.

A software-based approach for Real-Time Simulation (RTS) may have difficulties in meeting real-time constraints for complex models. In this thesis, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology to improve the response time of these models. Our methodology utilizes traditional Hardware/Software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator. We have optimized the hardware design such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement is obtained through the use of custom accelerators for common non-linear functions. Since the systems we examine have relatively low response time requirements, our approach greatly simplifies the software components by porting the computationally complex regions to hardware. We illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.

ISBN: 9781124431420Subjects--Topical Terms:

1669061
Engineering, Computer.

Real-time simulation of dynamic vehicle models using high performance reconfigurable computing platforms.
LDR:02657nam 2200301 4500 001 1403394
005 20111115085232.5
008 130515s2010 ||||||||||||||||| ||eng d
020 $a 9781124431420
035 $a (UMI)AAI1488058
035 $a AAI1488058
040 $a UMI $c UMI
100 1 $a Monga, Madhu. $3 1682651
245 1 0 $a Real-time simulation of dynamic vehicle models using high performance reconfigurable computing platforms.
300 $a 79 p.
500 $a Source: Masters Abstracts International, Volume: 49-03, page: 1941.
500 $a Adviser: Joseph Zambreno.
502 $a Thesis (M.S.)--Iowa State University, 2010.
520 $a A software-based approach for Real-Time Simulation (RTS) may have difficulties in meeting real-time constraints for complex models. In this thesis, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology to improve the response time of these models. Our methodology utilizes traditional Hardware/Software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator. We have optimized the hardware design such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement is obtained through the use of custom accelerators for common non-linear functions. Since the systems we examine have relatively low response time requirements, our approach greatly simplifies the software components by porting the computationally complex regions to hardware. We illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.
590 $a School code: 0097.
650 4 $a Engineering, Computer. $3 1669061
690 $a 0464
710 2 $a Iowa State University. $b Electrical and Computer Engineering. $3 1018524
773 0 $t Masters Abstracts International $g 49-03.
790 1 0 $a Zambreno, Joseph, $e advisor
790 1 0 $a Steward, Brian L. $e committee member
790 1 0 $a Kelkar, Atul G. $e committee member
790 1 0 $a Aliprantis, Dionysios C. $e committee member
790 $a 0097
791 $a M.S.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1488058