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Low power and reliability assessment...

Mohyuddin, Nasir.

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Low power and reliability assessment techniques for advanced processor design.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Low power and reliability assessment techniques for advanced processor design./
作者:	Mohyuddin, Nasir.
面頁冊數:	125 p.
附註:	Source: Dissertation Abstracts International, Volume: 71-09, Section: B, page: 5663.
Contained By:	Dissertation Abstracts International71-09B.
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3418125
ISBN:	9781124161440

Low power and reliability assessment techniques for advanced processor design.
Mohyuddin, Nasir.

Low power and reliability assessment techniques for advanced processor design. - 125 p.

Source: Dissertation Abstracts International, Volume: 71-09, Section: B, page: 5663.

Thesis (Ph.D.)--University of Southern California, 2010.

The rapid scaling of silicon technologies over the past decade has introduced some strenuous constraints for processor design. The technology progression has exacerbated the power problem which has further increased the necessity to consider design reliability. Static power dissipation that used to be negligible in past is expected to be a major component of overall processor dissipation. In this research, we present techniques that reduce both static and dynamic power dissipation in modern processors while not compromising the processor reliability as whole. We also present a tool BDEC that can be used to compare the reliability of different possible implementations of major processor functional units to choose more reliable implementations in future processor designs.

ISBN: 9781124161440Subjects--Topical Terms:

1669061
Engineering, Computer.

Low power and reliability assessment techniques for advanced processor design.
LDR:02940nam 2200325 4500 001 1403155
005 20111111141815.5
008 130515s2010 ||||||||||||||||| ||eng d
020 $a 9781124161440
035 $a (UMI)AAI3418125
035 $a AAI3418125
040 $a UMI $c UMI
100 1 $a Mohyuddin, Nasir. $3 1682403
245 1 0 $a Low power and reliability assessment techniques for advanced processor design.
300 $a 125 p.
500 $a Source: Dissertation Abstracts International, Volume: 71-09, Section: B, page: 5663.
500 $a Adviser: Massoud Pedram.
502 $a Thesis (Ph.D.)--University of Southern California, 2010.
520 $a The rapid scaling of silicon technologies over the past decade has introduced some strenuous constraints for processor design. The technology progression has exacerbated the power problem which has further increased the necessity to consider design reliability. Static power dissipation that used to be negligible in past is expected to be a major component of overall processor dissipation. In this research, we present techniques that reduce both static and dynamic power dissipation in modern processors while not compromising the processor reliability as whole. We also present a tool BDEC that can be used to compare the reliability of different possible implementations of major processor functional units to choose more reliable implementations in future processor designs.
520 $a The proposed techniques reduce both static and dynamic power dissipation in modern processor designs. While dealing with low power design one important design aspect is that the low power technique must not be power hungry itself. The beauty of the presented low power techniques is that they do not have huge hardware implementation cost, rather they use existing hardware to control power dissipation. Power dissipation overhead of presented techniques is minimal.
520 $a Smaller and smaller feature sizes and increased power density of modern processors which has resulted in high chip temperatures has increased the importance of reliability consideration in processor design. Since in future we will need to build reliable systems using unreliable components modern processor design will need to be geared towards considering design reliability during the early phases of the design. To help compare various design alternatives we developed a tool: BDEC which gives the reliability of a combinational circuit in terms of gate error probabilities and input error probabilities on the primary inputs.
590 $a School code: 0208.
650 4 $a Engineering, Computer. $3 1669061
690 $a 0464
710 2 $a University of Southern California. $b Electrical Engineering(VLSI Design). $3 1682404
773 0 $t Dissertation Abstracts International $g 71-09B.
790 1 0 $a Pedram, Massoud, $e advisor
790 1 0 $a Gupta, Sandeep $e committee member
790 1 0 $a Draper, Jeffrey T. $e committee member
790 1 0 $a Nakano, Aiichiro $e committee member
790 $a 0208
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3418125