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Energy efficient load latency tolera...

Hilton, Andrew D.

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Energy efficient load latency tolerance: Single-thread performance for the multi-core era.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Energy efficient load latency tolerance: Single-thread performance for the multi-core era./
Author:	Hilton, Andrew D.
Description:	183 p.
Notes:	Source: Dissertation Abstracts International, Volume: 72-05, Section: B, page: .
Contained By:	Dissertation Abstracts International72-05B.
Subject:	Engineering, Computer. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3447628
ISBN:	9781124531724

Energy efficient load latency tolerance: Single-thread performance for the multi-core era.
Hilton, Andrew D.

Energy efficient load latency tolerance: Single-thread performance for the multi-core era. - 183 p.

Source: Dissertation Abstracts International, Volume: 72-05, Section: B, page: .

Thesis (Ph.D.)--University of Pennsylvania, 2010.

Around 2003, newly activated power constraints caused single-thread performance growth to slow dramatically. The multi-core era was born with an emphasis on explicitly parallel software. Continuing to grow single-thread performance is still important in the multi-core context, but it must be done in an energy efficient way.

ISBN: 9781124531724Subjects--Topical Terms:

1669061
Engineering, Computer.

Energy efficient load latency tolerance: Single-thread performance for the multi-core era.
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100 1 $a Hilton, Andrew D. $3 1680250
245 1 0 $a Energy efficient load latency tolerance: Single-thread performance for the multi-core era.
300 $a 183 p.
500 $a Source: Dissertation Abstracts International, Volume: 72-05, Section: B, page: .
500 $a Advisers: Amir Roth; Milo Martin.
502 $a Thesis (Ph.D.)--University of Pennsylvania, 2010.
520 $a Around 2003, newly activated power constraints caused single-thread performance growth to slow dramatically. The multi-core era was born with an emphasis on explicitly parallel software. Continuing to grow single-thread performance is still important in the multi-core context, but it must be done in an energy efficient way.
520 $a One significant impediment to performance growth in both out-of-order and in-order processors is the long latency of last-level cache misses. Prior work introduced the idea of load latency tolerance---the ability to dynamically remove miss-dependent instructions from critical execution structures, continue execution under the miss, and re-execute miss-dependent instructions after the miss returns. However, previously proposed designs were unable to improve performance in an energy-efficient way---they introduced too many new large, complex structures and re-executed too many instructions.
520 $a This dissertation describes a new load latency tolerant design that is both energy-efficient, and applicable to both in-order and out-of-order cores. Key novel features include formulation of slice re-execution as an alternative use of multi-threading support, efficient schemes for register and memory state management, and new pruning mechanisms for drastically reducing load latency tolerance's dynamic execution overheads.
520 $a Area analysis shows that energy-efficient load latency tolerance increases the footprint of an out-of-order core by a few percent, while cycle-level simulation shows that it significantly improves the performance of memory-bound programs. Energy-efficient load latency tolerance is more energy-efficient than---and synergistic with---existing performance technique like dynamic voltage and frequency scaling (DVFS).
590 $a School code: 0175.
650 4 $a Engineering, Computer. $3 1669061
650 4 $a Computer Science. $3 626642
690 $a 0464
690 $a 0984
710 2 $a University of Pennsylvania. $3 1017401
773 0 $t Dissertation Abstracts International $g 72-05B.
790 1 0 $a Roth, Amir, $e advisor
790 1 0 $a Martin, Milo, $e advisor
790 $a 0175
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3447628