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Reduced-complexity VLSI architecture...

Kim, Sangmin.

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Reduced-complexity VLSI architectures for binary and nonbinary LDPC codes.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Reduced-complexity VLSI architectures for binary and nonbinary LDPC codes./
Author:	Kim, Sangmin.
Description:	122 p.
Notes:	Source: Dissertation Abstracts International, Volume: 71-10, Section: B, page: 6331.
Contained By:	Dissertation Abstracts International71-10B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3422570
ISBN:	9781124218915

Reduced-complexity VLSI architectures for binary and nonbinary LDPC codes.
Kim, Sangmin.

Reduced-complexity VLSI architectures for binary and nonbinary LDPC codes. - 122 p.

Source: Dissertation Abstracts International, Volume: 71-10, Section: B, page: 6331.

Thesis (Ph.D.)--University of Minnesota, 2010.

This thesis proposes efficient algorithm and architecture aspects for binary and nonbinary low-density parity-check (LDPC) codes by developing optimal quantization approaches, decoding algorithms, decoding schedules and switch networks based on the characteristics of specific codes. To provide a quantitative comparison with previous work, including design performance and cost, we implement and analyze our architectures using a Field Programmable Gate Array (FPGA) platform. The decoding of LDPC codes uses soft information, so it is important to analyze the error correcting performance with fixed-point computations. An adaptive quantization scheme to select suitable input values for the min-sum based decoding algorithm is given. Our simulation results show that it gives good error correcting performance compared with the conventional method. A reduced-complexity LDPC layered decoding architecture is proposed using an offset permutation scheme in the switch networks. Then, a switch network for the code rates defined in the IEEE 802.15.3c standard is optimized by reducing the number of control bits and eliminating unnecessary switch elements. We implement a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device and this design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz a maximum of 8 iterations. We propose an improved nonbinary decoding algorithm with a threshold factor to increase the performance of LDPC decoders. Implementing nonlinear functions as small look-up table leads us consider the dynamic range of the nonlinear functions in order to take more precisely into account the effect of finite precision computation. Finally, an efficient VLSI architecture for a nonbinary LDPC decoder will be presented.

ISBN: 9781124218915Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Reduced-complexity VLSI architectures for binary and nonbinary LDPC codes.
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100 1 $a Kim, Sangmin. $3 1672893
245 1 0 $a Reduced-complexity VLSI architectures for binary and nonbinary LDPC codes.
300 $a 122 p.
500 $a Source: Dissertation Abstracts International, Volume: 71-10, Section: B, page: 6331.
500 $a Adviser: Gerald E. Sobelman.
502 $a Thesis (Ph.D.)--University of Minnesota, 2010.
520 $a This thesis proposes efficient algorithm and architecture aspects for binary and nonbinary low-density parity-check (LDPC) codes by developing optimal quantization approaches, decoding algorithms, decoding schedules and switch networks based on the characteristics of specific codes. To provide a quantitative comparison with previous work, including design performance and cost, we implement and analyze our architectures using a Field Programmable Gate Array (FPGA) platform. The decoding of LDPC codes uses soft information, so it is important to analyze the error correcting performance with fixed-point computations. An adaptive quantization scheme to select suitable input values for the min-sum based decoding algorithm is given. Our simulation results show that it gives good error correcting performance compared with the conventional method. A reduced-complexity LDPC layered decoding architecture is proposed using an offset permutation scheme in the switch networks. Then, a switch network for the code rates defined in the IEEE 802.15.3c standard is optimized by reducing the number of control bits and eliminating unnecessary switch elements. We implement a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device and this design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz a maximum of 8 iterations. We propose an improved nonbinary decoding algorithm with a threshold factor to increase the performance of LDPC decoders. Implementing nonlinear functions as small look-up table leads us consider the dynamic range of the nonlinear functions in order to take more precisely into account the effect of finite precision computation. Finally, an efficient VLSI architecture for a nonbinary LDPC decoder will be presented.
590 $a School code: 0130.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a University of Minnesota. $b Electrical Engineering. $3 1018776
773 0 $t Dissertation Abstracts International $g 71-10B.
790 1 0 $a Sobelman, Gerald E., $e advisor
790 1 0 $a Parhi, Keshab K. $e committee member
790 1 0 $a Ebbini, Emad S. $e committee member
790 1 0 $a Garrett, Paul $e committee member
790 $a 0130
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3422570