東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Software-assisted hardware reliabili...

Janapa Reddi, Vijay.

Linked to FindBook

Google Book

Amazon

博客來

Software-assisted hardware reliability: Enabling aggressive timing speculation using run-time feedback from hardware and software.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Software-assisted hardware reliability: Enabling aggressive timing speculation using run-time feedback from hardware and software./
Author:	Janapa Reddi, Vijay.
Description:	171 p.
Notes:	Source: Dissertation Abstracts International, Volume: 71-07, Section: B, page: 4345.
Contained By:	Dissertation Abstracts International71-07B.
Subject:	Engineering, Computer. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3414768
ISBN:	9781124079677

Software-assisted hardware reliability: Enabling aggressive timing speculation using run-time feedback from hardware and software.
Janapa Reddi, Vijay.

Software-assisted hardware reliability: Enabling aggressive timing speculation using run-time feedback from hardware and software. - 171 p.

Source: Dissertation Abstracts International, Volume: 71-07, Section: B, page: 4345.

Thesis (Ph.D.)--Harvard University, 2010.

In the era of nanoscale technology scaling, we are facing the limits of physics, challenging robust and reliable microprocessor design and fabrication. As these trends continue, guaranteeing correctness of execution is becoming prohibitively expensive and impractical. In this thesis, we demonstrate the benefits of abstracting circuit-level challenges to the architecture and software layers. Reliability challenges are broadly classified into process, voltage, and thermal variations. As proof of concept, we target voltage variation, which is least understood, demonstrating its growing detrimental effects on future processors: Shrinking feature size and diminishing supply voltage are making circuits more sensitive to supply voltage fluctuations within the microprocessor. If left unattended, these voltage fluctuations can lead to timing violations or even transistor lifetime issues. This problem, more commonly known as the dI/dt problem, is forcing microprocessor designers to increasingly sacrifice processor performance, as well as power efficiency, in order to guarantee correctness and robustness of operation. Industry addresses this problem by un-optimizing the processor for the worst case voltage flux. Setting such extreme operating voltage margins for those large and infrequent voltage swings is not a sustainable solution in the long term. Therefore, we depart from this traditional strategy and operate the processor under more typical case conditions. We demonstrate that a collaborative architecture between hardware and software enables aggressive operating voltage margins, and as a consequence improves processor performance and power efficiency. This co-designed architecture is built on the principles of tolerance, avoidance and elimination. Using a fail-safe hardware mechanism to tolerate voltage margin violations, we enable timing speculation, while a run-time hardware and software layer attempts to not only predict and avoid impending violations, but also reschedules instructions and co-schedules threads intelligently to eliminate voltage violations altogether. We believe tolerance, avoidance and elimination are generalizable constructs capable of acting as guidelines to address and successfully mitigate the other parameter-related reliability challenges as well.

ISBN: 9781124079677Subjects--Topical Terms:

1669061
Engineering, Computer.

Software-assisted hardware reliability: Enabling aggressive timing speculation using run-time feedback from hardware and software.
LDR:03362nam 2200301 4500 001 1392587
005 20110218114620.5
008 130515s2010 ||||||||||||||||| ||eng d
020 $a 9781124079677
035 $a (UMI)AAI3414768
035 $a AAI3414768
040 $a UMI $c UMI
100 1 $a Janapa Reddi, Vijay. $3 1671046
245 1 0 $a Software-assisted hardware reliability: Enabling aggressive timing speculation using run-time feedback from hardware and software.
300 $a 171 p.
500 $a Source: Dissertation Abstracts International, Volume: 71-07, Section: B, page: 4345.
500 $a Advisers: David M. Brooks; Gu-Yeon Wei; Michael D. Smith.
502 $a Thesis (Ph.D.)--Harvard University, 2010.
520 $a In the era of nanoscale technology scaling, we are facing the limits of physics, challenging robust and reliable microprocessor design and fabrication. As these trends continue, guaranteeing correctness of execution is becoming prohibitively expensive and impractical. In this thesis, we demonstrate the benefits of abstracting circuit-level challenges to the architecture and software layers. Reliability challenges are broadly classified into process, voltage, and thermal variations. As proof of concept, we target voltage variation, which is least understood, demonstrating its growing detrimental effects on future processors: Shrinking feature size and diminishing supply voltage are making circuits more sensitive to supply voltage fluctuations within the microprocessor. If left unattended, these voltage fluctuations can lead to timing violations or even transistor lifetime issues. This problem, more commonly known as the dI/dt problem, is forcing microprocessor designers to increasingly sacrifice processor performance, as well as power efficiency, in order to guarantee correctness and robustness of operation. Industry addresses this problem by un-optimizing the processor for the worst case voltage flux. Setting such extreme operating voltage margins for those large and infrequent voltage swings is not a sustainable solution in the long term. Therefore, we depart from this traditional strategy and operate the processor under more typical case conditions. We demonstrate that a collaborative architecture between hardware and software enables aggressive operating voltage margins, and as a consequence improves processor performance and power efficiency. This co-designed architecture is built on the principles of tolerance, avoidance and elimination. Using a fail-safe hardware mechanism to tolerate voltage margin violations, we enable timing speculation, while a run-time hardware and software layer attempts to not only predict and avoid impending violations, but also reschedules instructions and co-schedules threads intelligently to eliminate voltage violations altogether. We believe tolerance, avoidance and elimination are generalizable constructs capable of acting as guidelines to address and successfully mitigate the other parameter-related reliability challenges as well.
590 $a School code: 0084.
650 4 $a Engineering, Computer. $3 1669061
650 4 $a Computer Science. $3 626642
690 $a 0464
690 $a 0984
710 2 $a Harvard University. $3 528741
773 0 $t Dissertation Abstracts International $g 71-07B.
790 1 0 $a Brooks, David M., $e advisor
790 1 0 $a Wei, Gu-Yeon, $e advisor
790 1 0 $a Smith, Michael D., $e advisor
790 $a 0084
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3414768