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Reducing the performance impact of e...

Kumar, Sumeet.

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Reducing the performance impact of ensuring soft error reliability in high performance microprocessors.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Reducing the performance impact of ensuring soft error reliability in high performance microprocessors./
作者:	Kumar, Sumeet.
面頁冊數:	160 p.
附註:	Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3225.
Contained By:	Dissertation Abstracts International71-05B.
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3402985
ISBN:	9781109758009

Reducing the performance impact of ensuring soft error reliability in high performance microprocessors.
Kumar, Sumeet.

Reducing the performance impact of ensuring soft error reliability in high performance microprocessors. - 160 p.

Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3225.

Thesis (Ph.D.)--State University of New York at Binghamton, 2010.

In this dissertation we identify the key reasons for the performance impact and energy impact of redundant multi-threading (RMT). We also propose various techniques to improve the performance and address the energy concerns of various flavors of RMT.

ISBN: 9781109758009Subjects--Topical Terms:

1669061
Engineering, Computer.

Reducing the performance impact of ensuring soft error reliability in high performance microprocessors.
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245 1 0 $a Reducing the performance impact of ensuring soft error reliability in high performance microprocessors.
300 $a 160 p.
500 $a Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3225.
500 $a Adviser: Aneesh Aggarwal.
502 $a Thesis (Ph.D.)--State University of New York at Binghamton, 2010.
520 $a In this dissertation we identify the key reasons for the performance impact and energy impact of redundant multi-threading (RMT). We also propose various techniques to improve the performance and address the energy concerns of various flavors of RMT.
520 $a In our first approach, we propose reducing resource redundancy as a means to mitigate the performance impact of redundancy. We investigate two techniques in this approach (i) register bits reuse technique that attempts to use the same register (but different bits) for both the copies of the same instruction, if the result produced by the instruction is of small size, and (ii) register value reuse technique that attempts to use the same register for a main instruction and a distinct redundant instruction, if both the instructions produce the same result. These techniques, along with some others, are used to reduce redundancy in register file, reorder buffer, and load/store buffer. The techniques are evaluated in terms of their performance, power, and vulnerability impact on an RMT processor. Our experiments show that the techniques achieve about 95% performance improvement and about 17% energy reduction. The vulnerability of the RMT remains the same with the techniques.
520 $a Our second approach proposes reducing instruction redundancy (the instructions that are redundantly executed) as a means to mitigate the performance and energy impact of redundancy. We experiment with an decoupled RMT approach where the frontend pipeline stages are protected through error codes, while the backend pipeline stages are protected through redundant execution. In this approach, we define two categories of instructions---self-checking and semi self-checking instructions. Self checking instructions are those instructions whose results are checked for any errors when their "main" copies are executed. These instructions are not redundantly executed. Semi self-checking instructions are those instructions for which a major part of their results is checked when the "main" copies are executed, and the remaining part of the instructions is checked using a small amount of additional hardware. Reducing instruction redundancy with this approach has the same fault coverage as the base architecture where all the instructions are redundantly executed. Our experiments show that the techniques reduce instruction redundancy by about 58% and recover about 51% of the performance lost due to redundant execution. Our techniques also recover about 40% of the energy consumption increase in the key data-path structures.
520 $a In our third approach, we explore speculative mechanisms to trade-off reliability for performance in RMT. Our basic approach validates the execution of an instruction by comparing its result against the expected result. Only those instructions are redundantly executed for which the validations fail. This mechanism is expected to have a minimal vulnerability impact because it is highly unlikely that an erroneous result matches the expected value. We also propose several extensions to the basic approach that further explore the performance-reliability trade-off design space. A combination of these techniques incur about 10% performance impact and about 0.09% undetected instruction error rate, compared to about 25% performance impact for RMT with no undetected errors.
520 $a Finally we propose selective redundancy to achieve optimal performance-reliability tradeoff. We show that RMT based tradeoff techniques are a sub-optimal design choice, as they duplicate an instruction in the entire pipeline. We show that each hardware structure in the pipeline has a different set of instructions contributing, the most, towards its AVF. We identify Instruction Criticality Factor (ICF) as the percentage AVF contribution of an instruction towards the total AVF of a particular hardware structure. We propose schemes which provide selective redundancy based on ICF. We observe that duplicating only few instructions, with high ICF values, reduces the AVF of the structure by a significant amount. Our results show that, for integer RF, providing redundancy to 23% of instructions, reduces its AVF by 80%, whereas for floating point RF duplicating 24% of entries reduces its AVF by 33%. For integer cluster of IQ 11% duplication reduces its AVF by 44%. Corresponding number for float cluster is, 43% reduction by duplicating 7% instructions. When ICF based selective redundancy is applied to both IQ and RF, performance reduces by 8% as compared to base single thread, while the error coverage remains the same. (Abstract shortened by UMI.)
590 $a School code: 0792.
650 4 $a Engineering, Computer. $3 1669061
690 $a 0464
710 2 $a State University of New York at Binghamton. $b Electrical Engineering. $3 1057631
773 0 $t Dissertation Abstracts International $g 71-05B.
790 1 0 $a Aggarwal, Aneesh, $e advisor
790 1 0 $a Wu, Qing $e committee member
790 1 0 $a Ponomarev, Dmitry $e committee member
790 $a 0792
791 $a Ph.D.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3402985