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Parallel-node low-density parity-che...

Brandon, Tyler.

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Parallel-node low-density parity-check convolutional code encoder and decoder architectures.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Parallel-node low-density parity-check convolutional code encoder and decoder architectures./
作者:	Brandon, Tyler.
面頁冊數:	205 p.
附註:	Source: Dissertation Abstracts International, Volume: 71-02, Section: B, page: 1198.
Contained By:	Dissertation Abstracts International71-02B.
標題:	Engineering, Computer. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=NR56595
ISBN:	9780494565957

Parallel-node low-density parity-check convolutional code encoder and decoder architectures.
Brandon, Tyler.

Parallel-node low-density parity-check convolutional code encoder and decoder architectures. - 205 p.

Source: Dissertation Abstracts International, Volume: 71-02, Section: B, page: 1198.

Thesis (Ph.D.)--University of Alberta (Canada), 2010.

We present novel architectures for parallel-node low-density parity-check convolutional code (PN-LDPC-CC) encoders and decoders. Based on a recently introduced implementation-aware class of LDPC-CCs, these encoders and decoders take advantage of increased node-parallelization to simultaneously decrease the energy-per-bit and increase the decoded information throughput. A series of progressively improved encoder and decoder designs are presented and characterized using synthesis results with respect to power, area and throughput. The best of the encoder and decoder designs significantly advance the state-of-the-art in terms of both the energy-per-bit and throughput/area metrics. One of the presented decoders, for an Eb/N0 of 2.5 dB has a bit-error-rate of 10-6, takes 4.5 mm2 in a CMOS 90-nm process, and achieves an energy-per-decoded-information-bit of 65 pJ and a decoded information throughput of 4.8 Gbits/s. We implement an earlier non-parallel node LDPC-CC encoder, decoder and a channel emulator in silicon. We provide readers, via two sets of tables, the ability to look up our decoder hardware metrics, across four different process technologies, for over 1000 variations of our PN-LDPC-CC decoders. By imposing practical decoder implementation constraints on power or area, which in turn drives trade-offs in code size versus the number of decoder processors, we compare the code BER performance. An extensive comparison to known LDPC-BC/CC decoder implementations is provided.

ISBN: 9780494565957Subjects--Topical Terms:

1669061
Engineering, Computer.

Parallel-node low-density parity-check convolutional code encoder and decoder architectures.
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