Hachtel, Gary D.
Overview
| Works: | 2 works in 0 publications in 0 languages | |
|---|---|---|
Titles
Logic synthesis and verification algorithms
by:
SpringerLink (Online service); Hachtel, Gary D.; Somenzi, Fabio.
(Language materials, printed)
Logic minimization algorithms for VLSI synthesis /
by:
Brayton, Robert King.; Hachtel, Gary D.; McMullen, Curtis T.; Sangiovanni-Vincentelli, Alberto L.
(Language materials, printed)