Radecka, Katarzyna.
概要
| 作品: | 2 作品在 0 項出版品 0 種語言 | |
|---|---|---|
書目資訊
Verification by error modeling = using testing techniques in hardware verification /
by:
Zilic, Zeljko.; NetLibrary, Inc.; Radecka, Katarzyna.
(書目-語言資料,印刷品)
Verification by error modeling : = using testing techniques in hardware verification
by:
Zilic, Zeljko.; SpringerLink (Online service); Radecka, Katarzyna.
(書目-語言資料,印刷品)